From: Ralf Baechle <ralf@linux-mips.org>
To: Adam Kiepul <Adam_Kiepul@pmc-sierra.com>
Cc: "'hadi@cyberus.ca'" <hadi@cyberus.ca>,
linux-mips@linux-mips.org, sibyte-users@bitmover.com
Subject: Re: [SiByte] RE: weird sb1250 behavior
Date: Fri, 28 May 2004 22:59:23 +0200 [thread overview]
Message-ID: <20040528205923.GA14682@linux-mips.org> (raw)
In-Reply-To: <9DFF23E1E33391449FDC324526D1F2590283C58B@sjc1exm02.pmc_nt.nt.pmc-sierra.bc.ca>
On Fri, May 28, 2004 at 01:11:38PM -0700, Adam Kiepul wrote:
> There is a possible cache line read-after-write pseudo-dependency that, along with the code alignment in terms of the instruction pair doublewords, may do something weird to the sb1250 pipeline. Just my guess.
memcpy's source deals with what probably is another instance of the same
effect:
#ifdef CONFIG_CPU_SB1
nop # improves slotting
#endif
Ralf
prev parent reply other threads:[~2004-05-28 21:02 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-05-28 20:11 weird sb1250 behavior Adam Kiepul
2004-05-28 20:59 ` Ralf Baechle [this message]
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