From: Ralf Baechle <ralf@linux-mips.org>
To: Johannes Stezenbach <js@convergence.de>,
Dominic Sweetman <dom@mips.com>,
Emmanuel Michon <em@realmagic.fr>,
linux-mips@linux-mips.org
Subject: Re: TLB dimensioning
Date: Thu, 2 Sep 2004 12:31:37 +0200 [thread overview]
Message-ID: <20040902103137.GB19884@linux-mips.org> (raw)
In-Reply-To: <20040902101957.GA7728@convergence.de>
On Thu, Sep 02, 2004 at 12:19:57PM +0200, Johannes Stezenbach wrote:
> Hm, the MIPS32 4K Processor Core Family Software User's Manual says:
>
> "...the 4Kc core contains a 3-entry instruction TLB (ITLB), a 3-entry
> data TLB(DTLB), and a 16 dual-entry joint TLB (JTLB) with variable page
> sizes."
>
> What exactly does that mean, and how does it rate performancewise?
> I'm just curious ;-)
The idea behind ITLB and DTLB is to enable parallel TLB lookups for
instruction and data translations in ITLB and DTLB yet not having to make
dual or even more ported JTLB. ITLB and DTLB are entirely managed in
hardware and therefore not visible [1] to the OS software and as such
not part of the architecture; only the JTLB is and it's what's usually
meant when documentation or we on this list are speaking of the TLB.
Probably most MIPS implementations since at least the R4600 had ITLB and
DTLB.
Ralf
[1] Except possibly during hazards but your supposed to avoid them :-)
next prev parent reply other threads:[~2004-09-02 10:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-09-01 10:07 TLB dimensioning Emmanuel Michon
2004-09-01 13:28 ` Dominic Sweetman
2004-09-01 23:35 ` Ralf Baechle
2004-09-02 12:25 ` Dominic Sweetman
2004-09-02 10:19 ` Johannes Stezenbach
2004-09-02 10:31 ` Ralf Baechle [this message]
2004-09-02 11:53 ` Dominic Sweetman
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