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Date: Thu, 4 Nov 2004 10:04:09 -0800
From: Manish Lachwani <mlachwani@prometheus.mvista.com>
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
Subject: [PATCH] Rm7000/Rm9000 cache code change for 64-bit
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Hi Ralf

Attached small change fixes Rm7000/Rm9000 cache code to compile for 64-bit. This has
been verified on the 2.6.10 kernel and tested on the Momentum Ocelot-3 board.

Please review 

Thanks
Manish Lachwani


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--- arch/mips/mm/sc-rm7k.c.orig	2004-11-04 09:27:09.000000000 -0800
+++ arch/mips/mm/sc-rm7k.c	2004-11-02 11:10:51.000000000 -0800
@@ -127,13 +127,13 @@
 		      ".set mips0\n\t"
 		      ".set reorder"
 		      :
-		      : "r" (KSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
+		      : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
 	}
 }
 
 static __init void rm7k_sc_enable(void)
 {
-	void (*func)(void) = (void *) KSEG1ADDR(&__rm7k_sc_enable);
+	void (*func)(void) = (void *) CKSEG1ADDR(&__rm7k_sc_enable);
 
 	if (read_c0_config() & 0x08)			/* CONF_SE */
 		return;

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