Index: arch/mips/au1000/common/setup.c
===================================================================
RCS file: /home/develop/cvs_private/linux-mips-exadron/arch/mips/au1000/common/setup.c,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 setup.c
--- a/arch/mips/au1000/common/setup.c	2 Jul 2005 06:45:44 -0000	1.1.1.1
+++ b/arch/mips/au1000/common/setup.c	16 Jul 2005 12:27:18 -0000
@@ -152,38 +152,3 @@
 	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
 	au_writel(0, SYS_TOYTRIM);
 }
-
-#if defined(CONFIG_64BIT_PHYS_ADDR)
-/* This routine should be valid for all Au1x based boards */
-phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-	u32 start, end;
-
-	/* Don't fixup 36 bit addresses */
-	if ((phys_addr >> 32) != 0) return phys_addr;
-
-#ifdef CONFIG_PCI
-	start = (u32)Au1500_PCI_MEM_START;
-	end = (u32)Au1500_PCI_MEM_END;
-	/* check for pci memory window */
-	if ((phys_addr >= start) && ((phys_addr + size) < end)) {
-		return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
-	}
-#endif
-
-	/* All Au1x SOCs have a pcmcia controller */
-	/* We setup our 32 bit pseudo addresses to be equal to the
-	 * 36 bit addr >> 4, to make it easier to check the address
-	 * and fix it.
-	 * The Au1x socket 0 phys attribute address is 0xF 4000 0000.
-	 * The pseudo address we use is 0xF400 0000. Any address over
-	 * 0xF400 0000 is a pcmcia pseudo address.
-	 */
-	if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) {
-		return (phys_t)(phys_addr << 4);
-	}
-
-	/* default nop */
-	return phys_addr;
-}
-#endif
Index: include/asm-mips/pgtable.h
===================================================================
RCS file: /home/develop/cvs_private/linux-mips-exadron/include/asm-mips/pgtable.h,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 pgtable.h
--- a/include/asm-mips/pgtable.h	2 Jul 2005 06:47:30 -0000	1.1.1.1
+++ b/include/asm-mips/pgtable.h	16 Jul 2005 12:27:39 -0000
@@ -17,6 +17,7 @@
 #endif
 
 #include <asm/pgtable-bits.h>
+#include <ioremap.h>
 
 #define PAGE_NONE	__pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
 #define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
@@ -360,7 +361,6 @@
 #endif
 
 #ifdef CONFIG_64BIT_PHYS_ADDR
-extern phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size);
 extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
 
 static inline int io_remap_page_range(struct vm_area_struct *vma,
Index: include/asm-mips/mach-au1x00/ioremap.h
===================================================================
RCS file: /home/develop/cvs_private/linux-mips-exadron/include/asm-mips/mach-au1x00/ioremap.h,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 ioremap.h
--- a/include/asm-mips/mach-au1x00/ioremap.h	2 Jul 2005 06:47:31 -0000	1.1.1.1
+++ b/include/asm-mips/mach-au1x00/ioremap.h	16 Jul 2005 12:27:39 -0000
@@ -11,7 +11,42 @@
 
 #include <linux/types.h>
 
-#ifndef CONFIG_64BIT_PHYS_ADDR
+#ifdef CONFIG_64BIT_PHYS_ADDR
+/* This routine should be valid for all Au1x based boards */
+static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+#ifdef CONFIG_PCI
+	u32 start, end;
+#endif
+
+	/* Don't fixup 36 bit addresses */
+	if ((phys_addr >> 32) != 0) return phys_addr;
+
+#ifdef CONFIG_PCI
+	start = (u32)Au1500_PCI_MEM_START;
+	end = (u32)Au1500_PCI_MEM_END;
+	/* check for pci memory window */
+	if ((phys_addr >= start) && ((phys_addr + size) < end)) {
+		return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
+	}
+#endif
+
+	/* All Au1x SOCs have a pcmcia controller */
+	/* We setup our 32 bit pseudo addresses to be equal to the
+	 * 36 bit addr >> 4, to make it easier to check the address
+	 * and fix it.
+	 * The Au1x socket 0 phys attribute address is 0xF 4000 0000.
+	 * The pseudo address we use is 0xF400 0000. Any address over
+	 * 0xF400 0000 is a pcmcia pseudo address.
+	 */
+	if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) {
+		return (phys_t)(phys_addr << 4);
+	}
+
+	/* default nop */
+	return phys_addr;
+}
+#else
 static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
 {
 	return phys_addr;