From: Thiemo Seufer <ths@networkno.de>
To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: linux-mips@linux-mips.org
Subject: Re: Performance bug in c-r4k.c cache handling code
Date: Mon, 19 Sep 2005 20:31:18 +0200 [thread overview]
Message-ID: <20050919183118.GH3386@hattusa.textio> (raw)
In-Reply-To: <20050920.015424.41632255.anemo@mba.ocn.ne.jp>
Atsushi Nemoto wrote:
> >>>>> On Mon, 19 Sep 2005 17:40:56 +0200, Thiemo Seufer <ths@networkno.de> said:
>
> ths> I found an performance bug in c-r4k.c:r4k_dma_cache_inv, where a
> ths> Hit_Writeback_Inv instead of Hit_Invalidate is done. Ralf
> ths> mentioned this is probably due to broken Hit_Invalidate cache ops
> ths> on some CPUs, does anybody have more information about this? The
> ths> appended patch works apparently fine on R4400, R4600v2.0, R5000.
>
> Just a question: Are there any performance advantage of using
> Hit_Invalidate instead of Hit_Writeback_Inv if the target line was
> CLEAN?
I wouldn't think so, but it depends on the particular implementation.
Thiemo
next prev parent reply other threads:[~2005-09-19 18:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-09-19 15:40 Performance bug in c-r4k.c cache handling code Thiemo Seufer
2005-09-19 16:54 ` Atsushi Nemoto
2005-09-19 18:31 ` Thiemo Seufer [this message]
2005-09-19 17:01 ` Maciej W. Rozycki
2005-09-20 9:09 ` Dominic Sweetman
2005-09-20 12:22 ` Ralf Baechle
2005-09-20 12:37 ` Maciej W. Rozycki
2005-09-20 13:18 ` Dominic Sweetman
2005-09-20 14:51 ` Maciej W. Rozycki
2005-09-19 17:31 ` peter fuerst
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