From: Peter Horton <pdh@colonel-panic.org>
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
Subject: [PATCH 2.6.X] Fix Cobalt PCI cache line sizes
Date: Sun, 29 Jan 2006 21:33:48 +0000 [thread overview]
Message-ID: <20060129213348.GA3503@colonel-panic.org> (raw)
Correct cache line sizes.
P.
Index: linux.git/arch/mips/pci/fixup-cobalt.c
===================================================================
--- linux.git.orig/arch/mips/pci/fixup-cobalt.c 2006-01-29 12:35:50.000000000 +0000
+++ linux.git/arch/mips/pci/fixup-cobalt.c 2006-01-29 12:36:59.000000000 +0000
@@ -52,7 +52,7 @@
pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
if (lt < 64)
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
@@ -69,7 +69,7 @@
* host bridge.
*/
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
/*
* The code described by the comment below has been removed
next reply other threads:[~2006-01-29 21:29 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-01-29 21:33 Peter Horton [this message]
2006-01-30 4:02 ` [PATCH 2.6.X] Fix Cobalt PCI cache line sizes Ralf Baechle
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