From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To: macro@linux-mips.org
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: [PATCH] fast path for rdhwr emulation for TLS
Date: Sat, 08 Jul 2006 01:43:39 +0900 (JST) [thread overview]
Message-ID: <20060708.014339.89274844.anemo@mba.ocn.ne.jp> (raw)
In-Reply-To: <20060708.011245.82794581.anemo@mba.ocn.ne.jp>
On Sat, 08 Jul 2006 01:12:45 +0900 (JST), Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:
> > For a VIVT I-cache this can result in a TLB exception. TLB handlers are
> > not currently prepared for being called at the exception level.
>
> Thanks, now I understand the problem. Are there any good solutions?
> Only I can think now is using handle_ri_slow for such CPUs.
Can we use Index_Load_Data_I to load the instruction code from icache?
Just an idea...
---
Atsushi Nemoto
next prev parent reply other threads:[~2006-07-07 16:42 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-07-07 15:00 [PATCH] fast path for rdhwr emulation for TLS Atsushi Nemoto
2006-07-07 15:22 ` Maciej W. Rozycki
2006-07-07 16:12 ` Atsushi Nemoto
2006-07-07 16:43 ` Atsushi Nemoto [this message]
2006-07-07 17:04 ` Maciej W. Rozycki
2006-07-07 18:22 ` Ralf Baechle
2006-07-07 16:58 ` Maciej W. Rozycki
2006-07-08 16:12 ` Atsushi Nemoto
2006-07-10 14:40 ` Atsushi Nemoto
2006-09-14 17:28 ` Ralf Baechle
2006-09-15 3:09 ` Atsushi Nemoto
2006-07-10 14:55 ` Atsushi Nemoto
2006-07-11 2:53 ` Daniel Jacobowitz
2006-07-11 3:20 ` Atsushi Nemoto
2006-09-08 17:39 ` Nigel Stephens
2006-09-09 13:56 ` Atsushi Nemoto
2006-09-10 22:30 ` Nigel Stephens
2006-09-11 5:04 ` Atsushi Nemoto
2006-09-11 8:50 ` Atsushi Nemoto
2006-09-11 9:49 ` Thiemo Seufer
2006-09-11 14:13 ` Atsushi Nemoto
2006-09-11 15:17 ` Thiemo Seufer
2006-09-11 13:09 ` Maciej W. Rozycki
2006-09-11 14:30 ` Atsushi Nemoto
2006-09-11 17:53 ` Maciej W. Rozycki
2006-09-12 1:55 ` Atsushi Nemoto
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