From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Jan 2007 23:42:50 +0000 (GMT) Received: from web7912.mail.in.yahoo.com ([202.86.4.88]:30377 "HELO web7912.mail.in.yahoo.com") by ftp.linux-mips.org with SMTP id S28578666AbXATXmp (ORCPT ); Sat, 20 Jan 2007 23:42:45 +0000 Received: (qmail 49128 invoked by uid 60001); 20 Jan 2007 23:42:37 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.co.in; h=Message-ID:X-YMail-OSG:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=Ispd8GIhxtzkK2h7ctDXyj32uVmiJpO9H01aGx9uIMMnU7zyPFnXtzFhCJ2O0WgpqI2zDHwSLEIpywVussH/dYggRDCzYG/ZpSgTrQA7wCBZCGrT8US4OZ+ZTodmUhUL2UFeXn8dlx6bwSsCOI6d3UrxMQNWOA5Tb7CbVKjZN3o= ; Message-ID: <20070120234237.49126.qmail@web7912.mail.in.yahoo.com> X-YMail-OSG: _7lwWTMVM1nASmcNO9JtJoz4jfjiWUkgDxjHWx5K3PKw_A1I9HuM3SSQd1HpjfnZuJd3b261ww51tU6Nw9NA9HCJvdfIaHN66joJ_fdhck8YURLPx667FHDPRMbh2i.8HOasozEMCMg30NgVtgJRb3Jvjw-- Received: from [206.40.46.114] by web7912.mail.in.yahoo.com via HTTP; Sat, 20 Jan 2007 23:42:37 GMT Date: Sat, 20 Jan 2007 23:42:37 +0000 (GMT) From: sathesh babu Subject: Running Linux on FPGA To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="0-1862169920-1169336557=:45458" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 13726 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sathesh_edara2003@yahoo.co.in Precedence: bulk X-list: linux-mips --0-1862169920-1169336557=:45458 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi, I am trying to run Linux-2.6.18.2 ( with preemption enable) kernel on FPGA board which has MIPS24KE processor runs at 12 MHZ. Programmed the timer to give interrupt at every 10msec. I am seeing some inconsistence behavior during boot up processor. Some times it stops after "NET: Registered protocol family 17" and "VFS: Mounted root (jffs2 filesystem).". Could some give some pointers why the behavior is random. Is it OK to program the timer to 10 msec? or should it be more. Thanks in advance. Regards, Sathesh --------------------------------- Here’s a new way to find what you're looking for - Yahoo! Answers --0-1862169920-1169336557=:45458 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit
Hi,
I am trying to run Linux-2.6.18.2 ( with preemption enable) kernel on FPGA board which has MIPS24KE processor runs at 12 MHZ. Programmed the timer to give interrupt at every 10msec.
I am seeing some inconsistence behavior during boot up processor. Some times it stops after "NET: Registered protocol family 17" and "VFS: Mounted root (jffs2 filesystem).".
Could some give some pointers why the behavior is random.
Is it OK to program the timer to 10 msec? or should it be more.
Thanks in advance.
Regards,
Sathesh

Here’s a new way to find what you're looking for - Yahoo! Answers --0-1862169920-1169336557=:45458-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Jan 2007 00:40:44 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:15245 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S28578857AbXAUAkm (ORCPT ); Sun, 21 Jan 2007 00:40:42 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l0L0F1rS010016; Sun, 21 Jan 2007 00:17:41 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l0L0Ewwq010015; Sun, 21 Jan 2007 00:14:58 GMT Date: Sun, 21 Jan 2007 00:14:58 +0000 From: Ralf Baechle To: sathesh babu Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: Running Linux on FPGA Message-ID: <20070121001457.GA9123@linux-mips.org> References: <20070120234237.49126.qmail@web7912.mail.in.yahoo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070120234237.49126.qmail@web7912.mail.in.yahoo.com> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 13727 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Jan 20, 2007 at 11:42:37PM +0000, sathesh babu wrote: > Hi, > I am trying to run Linux-2.6.18.2 ( with preemption enable) kernel on FPGA board which has MIPS24KE processor runs at 12 MHZ. Programmed the timer to give interrupt at every 10msec. > I am seeing some inconsistence behavior during boot up processor. Some times it stops after "NET: Registered protocol family 17" and "VFS: Mounted root (jffs2 filesystem).". > Could some give some pointers why the behavior is random. > Is it OK to program the timer to 10 msec? or should it be more. The overhead of timer interrupts at this low clockrate is significant so I recommend to minimize the timer interrupt rate as far as possible. This is really a tradeoff between latency and overhead and matters much less on hardcores which run at hundreds of MHz. For power sensitive applications lowering the interrupt rate can also help. And that's alredy pretty much what you need to know, that is a 10ms timer is fine. Btw, is this coincidentally on a CoreFPGA 2 or 3 CPU card on a Malta board? Ralf From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Jan 2007 09:59:41 +0000 (GMT) Received: from nf-out-0910.google.com ([64.233.182.188]:31147 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20040269AbXAUJ7g (ORCPT ); Sun, 21 Jan 2007 09:59:36 +0000 Received: by nf-out-0910.google.com with SMTP id l24so1036446nfc for ; Sun, 21 Jan 2007 01:59:36 -0800 (PST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=beta; h=received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=SiS58fKZ4VDCS0l0eI2e/iukXL+7fnz4K1J67aNkimS/x6cUtru7mnLWXkPQODZ554NLY1tJu2p9TggZhpaDmbNucHa0sYO3aH/CQ6Gn7VTsEpDkI8um1i78UJuCFKGDVjrtiKxvOPNH45Rd4t/XisZLX1x0sPEa/EjpIbOW5N0= Received: by 10.82.120.14 with SMTP id s14mr4010686buc.1169373575547; Sun, 21 Jan 2007 01:59:35 -0800 (PST) Received: by 10.82.135.2 with HTTP; Sun, 21 Jan 2007 01:59:35 -0800 (PST) Message-ID: <8355959a0701210159k2fcb2323s2d38f91a41fcb942@mail.gmail.com> Date: Sun, 21 Jan 2007 15:29:35 +0530 From: "Sunil Naidu" To: "Ralf Baechle" Subject: Re: Running Linux on FPGA Cc: linux-kernel@vger.kernel.org, "sathesh babu" , linux-mips@linux-mips.org In-Reply-To: <20070121001457.GA9123@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20070120234237.49126.qmail@web7912.mail.in.yahoo.com> <20070121001457.GA9123@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 13728 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akula2.shark@gmail.com Precedence: bulk X-list: linux-mips On 1/21/07, Ralf Baechle wrote: > > The overhead of timer interrupts at this low clockrate is significant > so I recommend to minimize the timer interrupt rate as far as possible. > This is really a tradeoff between latency and overhead and matters > much less on hardcores which run at hundreds of MHz. For power sensitive > applications lowering the interrupt rate can also help. And that's alredy > pretty much what you need to know, that is a 10ms timer is fine. > I have worked with FPGA Linux system which is reconfigurable on-the-fly by the 200Mhz ARM9 CPU running Debian Linux, Altera Cyclone II FPGA is included on my TS-7300 board. Advantage is, Altera FPGA and a dedicated high-speed bus between the CPU and FPGA provides a good design scope to provide many solutions. Coming to boot up (by an USB 1GB SD card), by doing enough software tuning bootup to a Linux prompt takes just 1.69 seconds after power-up. If I remember correctly, SD image will look at the state of jumper 6 (should be put ON), the full Debian bootup will be bypassed and the system will instead drop straight to a shell prompt. 1.69 seconds after power-on the serial console prompt is active and 2.41 seconds after power-on the video console is displayed. This software is based on Debian & has a vendor supplied Linux boot loader. Currently am working (slowly in free time) to bring the whole thing to FC6. Shall post the progres... > > Ralf ~Akula2 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Jan 2007 11:14:37 +0000 (GMT) Received: from mx.mips.com ([63.167.95.198]:13554 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S28579729AbXAULOb (ORCPT ); Sun, 21 Jan 2007 11:14:31 +0000 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id l0LBFLl0023736; Sun, 21 Jan 2007 03:15:21 -0800 (PST) Received: from grendel (grendel [192.168.236.16]) by mercury.mips.com (8.13.5/8.13.5) with SMTP id l0LBEH8j008054; Sun, 21 Jan 2007 03:14:17 -0800 (PST) Message-ID: <005101c73d4e$6bbf96d0$10eca8c0@grendel> From: "Kevin D. Kissell" To: "Sunil Naidu" , "Ralf Baechle" Cc: , "sathesh babu" , References: <20070120234237.49126.qmail@web7912.mail.in.yahoo.com> <20070121001457.GA9123@linux-mips.org> <8355959a0701210159k2fcb2323s2d38f91a41fcb942@mail.gmail.com> Subject: Re: Running Linux on FPGA Date: Sun, 21 Jan 2007 12:22:20 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1807 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1896 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 13729 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips > > The overhead of timer interrupts at this low clockrate is significant > > so I recommend to minimize the timer interrupt rate as far as possible. > > This is really a tradeoff between latency and overhead and matters > > much less on hardcores which run at hundreds of MHz. For power sensitive > > applications lowering the interrupt rate can also help. And that's alredy > > pretty much what you need to know, that is a 10ms timer is fine. > > > > I have worked with FPGA Linux system which is reconfigurable > on-the-fly by the 200Mhz ARM9 CPU running Debian Linux, Altera Cyclone > II FPGA is included on my TS-7300 board. Advantage is, Altera FPGA and > a dedicated high-speed bus between the CPU and FPGA provides a good > design scope to provide many solutions. What's your point here? A 200MHz hard ore won't see the issues under discussion. We're talking about systems where the CPU itself is "soft" and implemented in an FPGA. Regards, Kevin K. From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Jan 2007 21:33:00 +0000 (GMT) Received: from tmailer.gwdg.de ([134.76.10.23]:35019 "EHLO tmailer.gwdg.de") by ftp.linux-mips.org with ESMTP id S20046926AbXAUVcy (ORCPT ); Sun, 21 Jan 2007 21:32:54 +0000 Received: from linux01.gwdg.de ([134.76.13.21]) by mailer.gwdg.de with esmtps (TLSv1:AES256-SHA:256) (Exim 4.63) (envelope-from ) id 1H8kJ4-0005T7-Ce; Sun, 21 Jan 2007 22:32:54 +0100 Received: from linux01.gwdg.de (localhost [127.0.0.1]) by linux01.gwdg.de (8.13.3/8.13.3/SuSE Linux 0.7) with ESMTP id l0LLVPGR029370; Sun, 21 Jan 2007 22:31:27 +0100 Received: from localhost (jengelh@localhost) by linux01.gwdg.de (8.13.3/8.13.3/Submit) with ESMTP id l0LLVPDA029364; Sun, 21 Jan 2007 22:31:25 +0100 Date: Sun, 21 Jan 2007 22:31:25 +0100 (MET) From: Jan Engelhardt To: Ralf Baechle cc: sathesh babu , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: Running Linux on FPGA In-Reply-To: <20070121001457.GA9123@linux-mips.org> Message-ID: References: <20070120234237.49126.qmail@web7912.mail.in.yahoo.com> <20070121001457.GA9123@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: (clean) by exiscan+sophie Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 13730 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jengelh@linux01.gwdg.de Precedence: bulk X-list: linux-mips On Jan 21 2007 00:14, Ralf Baechle wrote: >On Sat, Jan 20, 2007 at 11:42:37PM +0000, sathesh babu wrote: > >> I am trying to run Linux-2.6.18.2 ( with preemption enable) >> kernel on FPGA board which has MIPS24KE processor runs at 12 >> MHZ. Programmed the timer to give interrupt at every 10msec. I >> am seeing some inconsistence behavior during boot up processor. >> Some times it stops after "NET: Registered protocol family 17" >> and "VFS: Mounted root (jffs2 filesystem).". Could some give >> some pointers why the behavior is random. Is it OK to program >> the timer to 10 msec? or should it be more. > >The overhead of timer interrupts at this low clockrate is >significant so I recommend to minimize the timer interrupt rate as >far as possible. This is really a tradeoff between latency and >overhead and matters much less on hardcores which run at hundreds of >MHz. Hm I've been running 2.6.13 on a 10/20 MHz (switchable) i386 @ 100 Hz before without any hangs during boot or operation. -`J' -- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Jan 2007 16:50:12 +0000 (GMT) Received: from mx.mips.com ([63.167.95.198]:54781 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S28574920AbXAVQuI (ORCPT ); Mon, 22 Jan 2007 16:50:08 +0000 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id l0MGp0eh025815; Mon, 22 Jan 2007 08:51:00 -0800 (PST) Received: from grendel (grendel [192.168.236.16]) by mercury.mips.com (8.13.5/8.13.5) with SMTP id l0MGnuHU007560; Mon, 22 Jan 2007 08:49:57 -0800 (PST) Message-ID: <01c201c73e46$7ac9d930$10eca8c0@grendel> From: "Kevin D. Kissell" To: "Jan Engelhardt" , "Ralf Baechle" Cc: "sathesh babu" , , References: <20070120234237.49126.qmail@web7912.mail.in.yahoo.com> <20070121001457.GA9123@linux-mips.org> Subject: Re: Running Linux on FPGA Date: Mon, 22 Jan 2007 17:58:00 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1807 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1896 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 13735 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips > On Jan 21 2007 00:14, Ralf Baechle wrote: > >On Sat, Jan 20, 2007 at 11:42:37PM +0000, sathesh babu wrote: > > > >> I am trying to run Linux-2.6.18.2 ( with preemption enable) > >> kernel on FPGA board which has MIPS24KE processor runs at 12 > >> MHZ. Programmed the timer to give interrupt at every 10msec. I > >> am seeing some inconsistence behavior during boot up processor. > >> Some times it stops after "NET: Registered protocol family 17" > >> and "VFS: Mounted root (jffs2 filesystem).". Could some give > >> some pointers why the behavior is random. Is it OK to program > >> the timer to 10 msec? or should it be more. > > > >The overhead of timer interrupts at this low clockrate is > >significant so I recommend to minimize the timer interrupt rate as > >far as possible. This is really a tradeoff between latency and > >overhead and matters much less on hardcores which run at hundreds of > >MHz. > > Hm I've been running 2.6.13 on a 10/20 MHz (switchable) i386 @ 100 Hz > before without any hangs during boot or operation. Interrupt service overhead varies a bit between architectures, but your observation isn't too surprising. While the 1000Hz Linux 2.6 default is just bad craziness for embedded cores and FPGA prototypes, I've only seen 100Hz be truly unusable for sub-megahertz hardware simulators, and then only when running virtual SMP kernels, where multiple virtual "CPUs" on the same core all had to perform timer interrupt service every clock interval, which multiplies the proportion of available cycles consumed. But even if the system boots and runs, it's pretty scary to look at the proportion of time that a 20MHz core spends in interrupt service with a HZ value of 100 or more. So on one hand I agree with Ralf that on slow systems, especially FPGA systems, one wants to keep the clock interrupt frequency down to no more than 100Hz as a general rule (less than 100 wouldn't compile on 2.6.9 without some minor patches, which took the minimum down to HZ=48, below which the various macros that depend on HZ start generating divide-by-zero problems), while on the other hand I agree with Jan that it's by no means certain that Satesh's problem is really one of too many clock interrupts. Regards, Kevin K. From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx.mips.com ([63.167.95.198]:13554 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S28579729AbXAULOb (ORCPT ); Sun, 21 Jan 2007 11:14:31 +0000 Message-ID: <005101c73d4e$6bbf96d0$10eca8c0@grendel> From: "Kevin D. Kissell" References: <20070120234237.49126.qmail@web7912.mail.in.yahoo.com> <20070121001457.GA9123@linux-mips.org> <8355959a0701210159k2fcb2323s2d38f91a41fcb942@mail.gmail.com> Subject: Re: Running Linux on FPGA Date: Sun, 21 Jan 2007 12:22:20 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org To: Sunil Naidu , Ralf Baechle Cc: linux-kernel@vger.kernel.org, sathesh babu , linux-mips@linux-mips.org Message-ID: <20070121112220.5Ak7XZkGAVVFYFsz8gKng509UyF0g4wwz1X9LDYeJ7c@z> > > The overhead of timer interrupts at this low clockrate is significant > > so I recommend to minimize the timer interrupt rate as far as possible. > > This is really a tradeoff between latency and overhead and matters > > much less on hardcores which run at hundreds of MHz. For power sensitive > > applications lowering the interrupt rate can also help. And that's alredy > > pretty much what you need to know, that is a 10ms timer is fine. > > > > I have worked with FPGA Linux system which is reconfigurable > on-the-fly by the 200Mhz ARM9 CPU running Debian Linux, Altera Cyclone > II FPGA is included on my TS-7300 board. Advantage is, Altera FPGA and > a dedicated high-speed bus between the CPU and FPGA provides a good > design scope to provide many solutions. What's your point here? A 200MHz hard ore won't see the issues under discussion. We're talking about systems where the CPU itself is "soft" and implemented in an FPGA. Regards, Kevin K. From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx.mips.com ([63.167.95.198]:54781 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S28574920AbXAVQuI (ORCPT ); Mon, 22 Jan 2007 16:50:08 +0000 Message-ID: <01c201c73e46$7ac9d930$10eca8c0@grendel> From: "Kevin D. Kissell" References: <20070120234237.49126.qmail@web7912.mail.in.yahoo.com> <20070121001457.GA9123@linux-mips.org> Subject: Re: Running Linux on FPGA Date: Mon, 22 Jan 2007 17:58:00 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org To: Jan Engelhardt , Ralf Baechle Cc: sathesh babu , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Message-ID: <20070122165800.i5dgAjEfAOoY0HKSmmriCslcYBl991nYGpUEPwjiXj4@z> > On Jan 21 2007 00:14, Ralf Baechle wrote: > >On Sat, Jan 20, 2007 at 11:42:37PM +0000, sathesh babu wrote: > > > >> I am trying to run Linux-2.6.18.2 ( with preemption enable) > >> kernel on FPGA board which has MIPS24KE processor runs at 12 > >> MHZ. Programmed the timer to give interrupt at every 10msec. I > >> am seeing some inconsistence behavior during boot up processor. > >> Some times it stops after "NET: Registered protocol family 17" > >> and "VFS: Mounted root (jffs2 filesystem).". Could some give > >> some pointers why the behavior is random. Is it OK to program > >> the timer to 10 msec? or should it be more. > > > >The overhead of timer interrupts at this low clockrate is > >significant so I recommend to minimize the timer interrupt rate as > >far as possible. This is really a tradeoff between latency and > >overhead and matters much less on hardcores which run at hundreds of > >MHz. > > Hm I've been running 2.6.13 on a 10/20 MHz (switchable) i386 @ 100 Hz > before without any hangs during boot or operation. Interrupt service overhead varies a bit between architectures, but your observation isn't too surprising. While the 1000Hz Linux 2.6 default is just bad craziness for embedded cores and FPGA prototypes, I've only seen 100Hz be truly unusable for sub-megahertz hardware simulators, and then only when running virtual SMP kernels, where multiple virtual "CPUs" on the same core all had to perform timer interrupt service every clock interval, which multiplies the proportion of available cycles consumed. But even if the system boots and runs, it's pretty scary to look at the proportion of time that a 20MHz core spends in interrupt service with a HZ value of 100 or more. So on one hand I agree with Ralf that on slow systems, especially FPGA systems, one wants to keep the clock interrupt frequency down to no more than 100Hz as a general rule (less than 100 wouldn't compile on 2.6.9 without some minor patches, which took the minimum down to HZ=48, below which the various macros that depend on HZ start generating divide-by-zero problems), while on the other hand I agree with Jan that it's by no means certain that Satesh's problem is really one of too many clock interrupts. Regards, Kevin K.