From: Daniel Jacobowitz <dan@debian.org>
To: David Daney <ddaney@avtrex.com>
Cc: Richard Sandiford <rsandifo@nildram.co.uk>,
GCC Mailing List <gcc@gcc.gnu.org>,
linux-mips@linux-mips.org
Subject: Re: MIPS atomic memory operations (A.K.A PR 33479).
Date: Tue, 18 Sep 2007 22:32:35 -0400 [thread overview]
Message-ID: <20070919023235.GA31042@caradoc.them.org> (raw)
In-Reply-To: <46F06980.4080500@avtrex.com>
On Tue, Sep 18, 2007 at 05:12:48PM -0700, David Daney wrote:
> I guess my basic question is: Should MIPS_COMPARE_AND_SWAP have a 'sync' after
> the 'sc'? I would have thought that 'sc' made the write visible to all CPUs,
> but on the SB1 it appears not to be the case.
Yes, a barrier of some sort is definitely necessary. I believe the
SB1 is weakly ordered, and the architecture spec permits both strong
and weak ordering; but it's been a while since I tried this.
--
Daniel Jacobowitz
CodeSourcery
next prev parent reply other threads:[~2007-09-19 2:33 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-19 0:12 MIPS atomic memory operations (A.K.A PR 33479) David Daney
2007-09-19 2:32 ` Daniel Jacobowitz [this message]
2007-09-19 8:45 ` Thiemo Seufer
2007-09-19 16:58 ` Ralf Baechle
2007-09-19 17:07 ` Maciej W. Rozycki
2007-09-19 17:26 ` David Daney
2007-09-19 17:46 ` Maciej W. Rozycki
2007-09-19 17:49 ` David Daney
2007-09-19 18:12 ` Thiemo Seufer
2007-09-19 18:28 ` Ralf Baechle
2007-09-19 17:47 ` David Daney
2007-09-19 18:08 ` Maciej W. Rozycki
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