From: Ralf Baechle <ralf@linux-mips.org>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: Giuseppe Sacco <giuseppe@eppesuigoccas.homedns.org>,
linux-mips@linux-mips.org
Subject: Re: [PATCH] enable PCI bridges in MIPS ip32
Date: Thu, 4 Oct 2007 17:55:46 +0100 [thread overview]
Message-ID: <20071004165546.GA23610@linux-mips.org> (raw)
In-Reply-To: <Pine.LNX.4.64N.0710041459270.10573@blysk.ds.pg.gda.pl>
On Thu, Oct 04, 2007 at 03:13:01PM +0100, Maciej W. Rozycki wrote:
> > I think historically we had something like chkslot() first in the code
> > for the Galileo/Marvell bridges where it's needed due the brainddead
> > abuse of device 31 - any access to that will crash the system. From that
> > point on chkslot checking spread across the PCI code like the measles in
> > a kindergarden.
>
> Does the Galileo/Marvell do anything else with the device #31 than what
> is recommended by the PCI spec as a way to issue special cycles? We need
> to be careful about the device #31 in general; it is seldom used anyway as
> there are only 20 IDSEL lines defined by the standard and they are usually
> mapped starting from the device #0.
It's documented somewhere in their specs. Whatever, it ends crashing
the system so device 31 is hands off.
Ralf
next prev parent reply other threads:[~2007-10-04 16:55 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-10-04 10:32 [PATCH] enable PCI bridges in MIPS ip32 Giuseppe Sacco
2007-10-04 12:27 ` Maciej W. Rozycki
2007-10-04 12:50 ` Giuseppe Sacco
2007-10-04 13:03 ` Ralf Baechle
2007-10-04 14:13 ` Maciej W. Rozycki
2007-10-04 16:55 ` Ralf Baechle [this message]
2007-10-05 12:10 ` Maciej W. Rozycki
2007-10-05 12:27 ` Maciej W. Rozycki
2007-10-04 14:33 ` Giuseppe Sacco
2007-10-04 15:03 ` Maciej W. Rozycki
2007-10-04 15:19 ` Ralf Baechle
2007-10-04 15:27 ` Maciej W. Rozycki
2007-10-04 15:32 ` Ralf Baechle
2007-10-05 5:33 ` Giuseppe Sacco
2007-10-05 11:53 ` Maciej W. Rozycki
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