From: tsbogend@alpha.franken.de (Thomas Bogendoerfer)
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: ralf@linux-mips.org, ths@networkno.de, linux-mips@linux-mips.org,
michael@free-electrons.com
Subject: Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec
Date: Wed, 10 Sep 2008 10:31:57 +0200 [thread overview]
Message-ID: <20080910083157.GA6286@alpha.franken.de> (raw)
In-Reply-To: <1220948125-3550-1-git-send-email-thomas.petazzoni@free-electrons.com>
On Tue, Sep 09, 2008 at 10:15:25AM +0200, Thomas Petazzoni wrote:
> + else {
> + clear_c0_cause(CAUSEF_IV);
> + }
so we now touch a bit, which is at least marked reserved for R10k CPUs
and hope nobody did something else with it ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2008-09-10 8:32 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-09 8:15 [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec Thomas Petazzoni
2008-09-10 8:31 ` Thomas Bogendoerfer [this message]
2008-09-10 11:11 ` Kevin D. Kissell
2008-09-10 11:50 ` Ralf Baechle
2008-09-10 15:28 ` Shinya Kuribayashi
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