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From:	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
Date:	Sat, 27 Sep 2008 18:19:19 +0200
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	linux-ide@vger.kernel.org, ralf@linux-mips.org,
	Tejun Heo <htejun@gmail.com>
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On Friday 12 September 2008, Atsushi Nemoto wrote:
> On Fri, 12 Sep 2008 19:34:06 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:

[...]

> > >>>+	__ide_flush_dcache_range((unsigned long)addr, size);
> > 
> > >>   Why is this needed BTW?
> > 
> > > Do you mean __ide_flush_dcache_range?  This is needed to avoid cache
> > > inconsistency on PIO drive.  PIO transfer only writes to cache but
> > > upper layers expects the data is in main memory.
> > 
> >     Hum, then I wonder why it's MIPS specific...
> 
> SPARC also have it.  And there were some discussions for ARM IIRC.

I was under the impression that it has been addressed by Tejun at
the higher-layer level (for both ide/libata) long time ago and that
MIPS/SPARC code are just a left-overs which could be removed now?

Thanks,
Bart