* [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus.
@ 2008-12-17 20:44 David Daney
2008-12-17 21:20 ` David Daney
2008-12-18 8:07 ` Ralf Baechle
0 siblings, 2 replies; 7+ messages in thread
From: David Daney @ 2008-12-17 20:44 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney
Some CPUs implement mipsr2, but because they are a super-set of
mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into
this category. We would still like to use the optimized
implementation, so since we have already checked for
CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
CONFIG_CPU_MIPS64_R2 is sufficient.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/byteorder.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
index 2988d29..92ec1e1 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -46,7 +46,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
}
#define __arch_swab32 __arch_swab32
-#ifdef CONFIG_CPU_MIPS64_R2
+#ifdef CONFIG_64BIT
static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
{
__asm__(
--
1.5.6.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus.
2008-12-17 20:44 [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus David Daney
@ 2008-12-17 21:20 ` David Daney
2008-12-18 8:07 ` Ralf Baechle
1 sibling, 0 replies; 7+ messages in thread
From: David Daney @ 2008-12-17 21:20 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips
David Daney wrote:
> Some CPUs implement mipsr2, but because they are a super-set of
> mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into
> this category. We would still like to use the optimized
> implementation, so since we have already checked for
> CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
> CONFIG_CPU_MIPS64_R2 is sufficient.
>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
> arch/mips/include/asm/byteorder.h | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
> index 2988d29..92ec1e1 100644
> --- a/arch/mips/include/asm/byteorder.h
> +++ b/arch/mips/include/asm/byteorder.h
> @@ -46,7 +46,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
> }
> #define __arch_swab32 __arch_swab32
>
> -#ifdef CONFIG_CPU_MIPS64_R2
> +#ifdef CONFIG_64BIT
> static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
> {
> __asm__(
Although this patch is correct, it is not sufficient. The
implementation of __arch_swab64 is incorrect and unusable.
My next patch, which fixes it, should probably be applied before this
one.
David Daney
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus.
2008-12-17 20:44 [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus David Daney
2008-12-17 21:20 ` David Daney
@ 2008-12-18 8:07 ` Ralf Baechle
2008-12-18 16:42 ` David Daney
1 sibling, 1 reply; 7+ messages in thread
From: Ralf Baechle @ 2008-12-18 8:07 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips
On Wed, Dec 17, 2008 at 12:44:04PM -0800, David Daney wrote:
> Some CPUs implement mipsr2, but because they are a super-set of
> mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into
> this category. We would still like to use the optimized
> implementation, so since we have already checked for
> CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
> CONFIG_CPU_MIPS64_R2 is sufficient.
>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
> arch/mips/include/asm/byteorder.h | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
> index 2988d29..92ec1e1 100644
> --- a/arch/mips/include/asm/byteorder.h
> +++ b/arch/mips/include/asm/byteorder.h
> @@ -46,7 +46,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
> }
> #define __arch_swab32 __arch_swab32
>
> -#ifdef CONFIG_CPU_MIPS64_R2
> +#ifdef CONFIG_64BIT
This breaks every non-R2 64-bit processor.
Ralf
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus.
2008-12-18 8:07 ` Ralf Baechle
@ 2008-12-18 16:42 ` David Daney
2008-12-18 17:06 ` Ralf Baechle
0 siblings, 1 reply; 7+ messages in thread
From: David Daney @ 2008-12-18 16:42 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips
Ralf Baechle wrote:
> On Wed, Dec 17, 2008 at 12:44:04PM -0800, David Daney wrote:
>
>> Some CPUs implement mipsr2, but because they are a super-set of
>> mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into
>> this category. We would still like to use the optimized
>> implementation, so since we have already checked for
>> CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
>> CONFIG_CPU_MIPS64_R2 is sufficient.
>>
>> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
>> ---
>> arch/mips/include/asm/byteorder.h | 2 +-
>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
>> index 2988d29..92ec1e1 100644
>> --- a/arch/mips/include/asm/byteorder.h
>> +++ b/arch/mips/include/asm/byteorder.h
>> @@ -46,7 +46,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
>> }
>> #define __arch_swab32 __arch_swab32
>>
>> -#ifdef CONFIG_CPU_MIPS64_R2
>> +#ifdef CONFIG_64BIT
>
> This breaks every non-R2 64-bit processor.
>
I disagree. As I said before, the entire block is wrapped by #ifdef
MIPS_R2. non-R2 processors will not get any of the optimized byte
swapping code. I just want to allow all 64 bit R2 processors to use the
optimized code.
David Daney
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus.
2008-12-18 16:42 ` David Daney
@ 2008-12-18 17:06 ` Ralf Baechle
0 siblings, 0 replies; 7+ messages in thread
From: Ralf Baechle @ 2008-12-18 17:06 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips
On Thu, Dec 18, 2008 at 08:42:07AM -0800, David Daney wrote:
>> This breaks every non-R2 64-bit processor.
>>
> I disagree. As I said before, the entire block is wrapped by #ifdef
> MIPS_R2. non-R2 processors will not get any of the optimized byte
> swapping code. I just want to allow all 64 bit R2 processors to use the
> optimized code.
Whops sorry. I missed that this was wrapped into yet another #ifdef.
Ralf
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus.
@ 2009-06-26 16:02 David Daney
2009-06-28 18:50 ` Ralf Baechle
0 siblings, 1 reply; 7+ messages in thread
From: David Daney @ 2009-06-26 16:02 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney
Some CPUs implement mipsr2, but because they are a super-set of
mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into
this category. We would still like to use the optimized
implementation, so since we have already checked for
CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
CONFIG_CPU_MIPS64_R2 is sufficient.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/swab.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/swab.h b/arch/mips/include/asm/swab.h
index 99993c0..e5b9161 100644
--- a/arch/mips/include/asm/swab.h
+++ b/arch/mips/include/asm/swab.h
@@ -38,7 +38,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
}
#define __arch_swab32 __arch_swab32
-#ifdef CONFIG_CPU_MIPS64_R2
+#ifdef CONFIG_64BIT
static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
{
__asm__(
--
1.6.0.6
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus.
2009-06-26 16:02 David Daney
@ 2009-06-28 18:50 ` Ralf Baechle
0 siblings, 0 replies; 7+ messages in thread
From: Ralf Baechle @ 2009-06-28 18:50 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips
On Fri, Jun 26, 2009 at 09:02:48AM -0700, David Daney wrote:
> Some CPUs implement mipsr2, but because they are a super-set of
> mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into
> this category. We would still like to use the optimized
> implementation, so since we have already checked for
> CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
> CONFIG_CPU_MIPS64_R2 is sufficient.
>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
> arch/mips/include/asm/swab.h | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/mips/include/asm/swab.h b/arch/mips/include/asm/swab.h
> index 99993c0..e5b9161 100644
> --- a/arch/mips/include/asm/swab.h
> +++ b/arch/mips/include/asm/swab.h
> @@ -38,7 +38,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
> }
> #define __arch_swab32 __arch_swab32
>
> -#ifdef CONFIG_CPU_MIPS64_R2
> +#ifdef CONFIG_64BIT
You just broke support for non-R2 64-bit processors.
Ralf
^ permalink raw reply [flat|nested] 7+ messages in thread
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2008-12-17 20:44 [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus David Daney
2008-12-17 21:20 ` David Daney
2008-12-18 8:07 ` Ralf Baechle
2008-12-18 16:42 ` David Daney
2008-12-18 17:06 ` Ralf Baechle
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2009-06-28 18:50 ` Ralf Baechle
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