[PATCH 0/3] MIPS: Extend plat_* abstractions, cache support

[PATCH 0/3] MIPS: Extend plat_* abstractions, cache support

[Kevin Cernekee]

Hi,

I am upgrading an SoC to the 2.6.29.1 kernel from an earlier version,
and in the process I am switching over the old board support
customizations to use the newer, cleaner plat_* functions.  I found two
cases where the plat_* functions did not provide enough information,
so I had to modify the API:

plat_unmap_dma_mem() - Our handler needs to know the size and direction
of the DMA mapping.  This information is not encoded in the DMA address,
so it needed to be passed in explicitly.

plat_dma_addr_to_phys() - The bus<->physical address mappings differ
based on which bus is being used.  It is not always possible to infer
which bus is being used from the bus address alone, so I added a
"struct device" to the function definition.

Also, our MIPS core uses 64-byte D$ lines, so I needed to generate the
corresponding blast* functions.

These patches apply against the linux-mips.org GIT tree.

[PATCH 1/3] MIPS: Add size and direction arguments to plat_unmap_dma_mem()

[Kevin Cernekee]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 .../include/asm/mach-cavium-octeon/dma-coherence.h |    3 ++-
 arch/mips/include/asm/mach-generic/dma-coherence.h |    3 ++-
 arch/mips/include/asm/mach-ip27/dma-coherence.h    |    3 ++-
 arch/mips/include/asm/mach-ip32/dma-coherence.h    |    3 ++-
 arch/mips/include/asm/mach-jazz/dma-coherence.h    |    3 ++-
 arch/mips/include/asm/mach-lemote/dma-coherence.h  |    3 ++-
 arch/mips/mm/dma-default.c                         |    8 ++++----
 7 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index f30fce9..7289e67 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -35,7 +35,8 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
 	return dma_addr;
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, enum dma_data_direction direction)
 {
 	octeon_unmap_dma_mem(dev, dma_addr);
 }
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 36c611b..804c2de 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -28,7 +28,8 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
 	return dma_addr;
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, enum dma_data_direction direction)
 {
 }
 
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 4c21bfc..8676673 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -38,7 +38,8 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
 	return dma_addr & ~(0xffUL << 56);
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, enum dma_data_direction direction)
 {
 }
 
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 7ae40f4..d41805e 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -60,7 +60,8 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
 	return addr;
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, enum dma_data_direction direction)
 {
 }
 
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index 1c7cd27..5f3d7ea 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -27,7 +27,8 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
 	return vdma_log2phys(dma_addr);
 }
 
-static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, enum dma_data_direction direction)
 {
 	vdma_free(dma_addr);
 }
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index 38fad7d..c78f1d8 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -30,7 +30,8 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
 	return dma_addr & 0x7fffffff;
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, enum dma_data_direction direction)
 {
 }
 
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 4fdb7f5..30b108c 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -111,7 +111,7 @@ EXPORT_SYMBOL(dma_alloc_coherent);
 void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
 	dma_addr_t dma_handle)
 {
-	plat_unmap_dma_mem(dev, dma_handle);
+	plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
 	free_pages((unsigned long) vaddr, get_order(size));
 }
 
@@ -122,7 +122,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 {
 	unsigned long addr = (unsigned long) vaddr;
 
-	plat_unmap_dma_mem(dev, dma_handle);
+	plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
 
 	if (!plat_device_is_coherent(dev))
 		addr = CAC_ADDR(addr);
@@ -173,7 +173,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 		__dma_sync(dma_addr_to_virt(dma_addr), size,
 		           direction);
 
-	plat_unmap_dma_mem(dev, dma_addr);
+	plat_unmap_dma_mem(dev, dma_addr, size, direction);
 }
 
 EXPORT_SYMBOL(dma_unmap_single);
@@ -232,7 +232,7 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
 			if (addr)
 				__dma_sync(addr, sg->length, direction);
 		}
-		plat_unmap_dma_mem(dev, sg->dma_address);
+		plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction);
 	}
 }
 
-- 
1.5.3.6

[PATCH 2/3] MIPS: Pass struct device to plat_dma_addr_to_phys()

[Kevin Cernekee]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 .../include/asm/mach-cavium-octeon/dma-coherence.h |    3 ++-
 arch/mips/include/asm/mach-generic/dma-coherence.h |    3 ++-
 arch/mips/include/asm/mach-ip27/dma-coherence.h    |    3 ++-
 arch/mips/include/asm/mach-ip32/dma-coherence.h    |    3 ++-
 arch/mips/include/asm/mach-jazz/dma-coherence.h    |    3 ++-
 arch/mips/include/asm/mach-lemote/dma-coherence.h  |    3 ++-
 arch/mips/mm/dma-default.c                         |   15 ++++++++-------
 7 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index 7289e67..17d5794 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -30,7 +30,8 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
 	return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
 }
 
-static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr)
 {
 	return dma_addr;
 }
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 804c2de..8da9807 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -23,7 +23,8 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
 	return page_to_phys(page);
 }
 
-static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr)
 {
 	return dma_addr;
 }
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 8676673..d3d0401 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -33,7 +33,8 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
 	return pa;
 }
 
-static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr)
 {
 	return dma_addr & ~(0xffUL << 56);
 }
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index d41805e..3785595 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -50,7 +50,8 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
 }
 
 /* This is almost certainly wrong but it's what dma-ip32.c used to use  */
-static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr)
 {
 	unsigned long addr = dma_addr & RAM_OFFSET_MASK;
 
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index 5f3d7ea..f93aee5 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -22,7 +22,8 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
 	return vdma_alloc(page_to_phys(page), PAGE_SIZE);
 }
 
-static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr)
 {
 	return vdma_log2phys(dma_addr);
 }
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index c78f1d8..c8de5e7 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -25,7 +25,8 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
 	return page_to_phys(page) | 0x80000000;
 }
 
-static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr)
 {
 	return dma_addr & 0x7fffffff;
 }
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 30b108c..7e48e76 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -20,9 +20,10 @@
 
 #include <dma-coherence.h>
 
-static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr)
+static inline unsigned long dma_addr_to_virt(struct device *dev,
+	dma_addr_t dma_addr)
 {
-	unsigned long addr = plat_dma_addr_to_phys(dma_addr);
+	unsigned long addr = plat_dma_addr_to_phys(dev, dma_addr);
 
 	return (unsigned long)phys_to_virt(addr);
 }
@@ -170,7 +171,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 	enum dma_data_direction direction)
 {
 	if (cpu_is_noncoherent_r10000(dev))
-		__dma_sync(dma_addr_to_virt(dma_addr), size,
+		__dma_sync(dma_addr_to_virt(dev, dma_addr), size,
 		           direction);
 
 	plat_unmap_dma_mem(dev, dma_addr, size, direction);
@@ -246,7 +247,7 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 	if (cpu_is_noncoherent_r10000(dev)) {
 		unsigned long addr;
 
-		addr = dma_addr_to_virt(dma_handle);
+		addr = dma_addr_to_virt(dev, dma_handle);
 		__dma_sync(addr, size, direction);
 	}
 }
@@ -262,7 +263,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
 	if (!plat_device_is_coherent(dev)) {
 		unsigned long addr;
 
-		addr = dma_addr_to_virt(dma_handle);
+		addr = dma_addr_to_virt(dev, dma_handle);
 		__dma_sync(addr, size, direction);
 	}
 }
@@ -277,7 +278,7 @@ void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
 	if (cpu_is_noncoherent_r10000(dev)) {
 		unsigned long addr;
 
-		addr = dma_addr_to_virt(dma_handle);
+		addr = dma_addr_to_virt(dev, dma_handle);
 		__dma_sync(addr + offset, size, direction);
 	}
 }
@@ -293,7 +294,7 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
 	if (!plat_device_is_coherent(dev)) {
 		unsigned long addr;
 
-		addr = dma_addr_to_virt(dma_handle);
+		addr = dma_addr_to_virt(dev, dma_handle);
 		__dma_sync(addr + offset, size, direction);
 	}
 }
-- 
1.5.3.6

[PATCH 3/3] MIPS: Support 64-byte D-cache line size

[Kevin Cernekee]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/include/asm/r4kcache.h |    1 +
 arch/mips/mm/c-r4k.c             |   12 ++++++++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 4c140db..387bf59 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -399,6 +399,7 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 171951d..71fe4cb 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -100,6 +100,12 @@ static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 	blast_dcache32_page(addr);
 }
 
+static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
+{
+	R4600_HIT_CACHEOP_WAR_IMPL;
+	blast_dcache64_page(addr);
+}
+
 static void __cpuinit r4k_blast_dcache_page_setup(void)
 {
 	unsigned long  dc_lsize = cpu_dcache_line_size();
@@ -110,6 +116,8 @@ static void __cpuinit r4k_blast_dcache_page_setup(void)
 		r4k_blast_dcache_page = blast_dcache16_page;
 	else if (dc_lsize == 32)
 		r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
+	else if (dc_lsize == 64)
+		r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 }
 
 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
@@ -124,6 +132,8 @@ static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
 		r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 	else if (dc_lsize == 32)
 		r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
+	else if (dc_lsize == 64)
+		r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 }
 
 static void (* r4k_blast_dcache)(void);
@@ -138,6 +148,8 @@ static void __cpuinit r4k_blast_dcache_setup(void)
 		r4k_blast_dcache = blast_dcache16;
 	else if (dc_lsize == 32)
 		r4k_blast_dcache = blast_dcache32;
+	else if (dc_lsize == 64)
+		r4k_blast_dcache = blast_dcache64;
 }
 
 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
-- 
1.5.3.6

Re: [PATCH 0/3] MIPS: Extend plat_* abstractions, cache support

[Bob Zhang]

Now , I have ported suspend2 code (based on 2.4.21 patch) into mips
architecture, my kernel version is 2.4.21.

My Environment:
kernel:2.4.21
Architecture:mips 32: 4KEc
tty device : only has a serial port.



Now, we have finish 99% work-load, but at last ,we found a problem,
kernel panic after resume code has been executed completely , kernel
code has return the code after hibernate. but system have not return
console, it happened kernel panic.

in resume code, I added debugging code, I am sure, resume code has
been executed completely.
including ,reading pageset1 and pageset2,and copy kernel to original
location, restore cpu context and unfroze processes.

Could you please give me some ideas and suggestions ? thanks very much!


----------
Error output is like this;

Waking     5: bdflush.
Waking     6: kupdated.
Waking     7: mtdblockd.
Waking     8: khubd.
Waking    65: lircd.
Waking    67: inetd.
Waking    80: pure-ftpd.
Waking    81: sh.
Waking    86: hibernate.
Waking   163: hibernate.
Waking   164: tee.
About to restore original console.
swsusp_default_console_level = 1
console_loglevel=7
default_message_loglevel = 4
orig_default_message_loglevel=0
at end of do_software_suspend
Kernel unaligned instruction access in unaligned.c::do_ade, line 446:

CPU Regs : ===========================================================
$0 : 00000000 80290000 00000100 fffdffff 00000007 00000006 802342cc 820e83d4
$8 : 00000000 00000000 00000000 820e83dc 820e83f4 820e8000 80278010 00000000
$16: 8028f7b8 0000debe 00001ebe 802a53a0 0000dee0 7fff7d48 00000004 00000014
$24: 8200000c 2abe4090                   820e8000 820e9e70 00000000 0000000a
Hi : 0000007a
Lo : 000000b7
epc   : 0000000a    Tainted: G Z
Status: 10008403
Cause : 10800010
PrId  : 0001906c
Process init (pid: 1, stackpage=820e8000)
show_stack ============================================================
Stack:    80287ce0 0000003e 0000003c 800b93cc 00000000 00000400 80111bb0
 00000000 00001ee0 ffffffff 0000dee0 10008400 00000001 800b9460 0000000b
 00000189 00000004 00000001 10008400 802a4fc4 80287cf0 10008400 00000001
 0000000a 80287ce0 0000003c 800b9ac0 800b99bc 80239200 10008400 802391bc
 80239200 802a4fc2 802a4fc4 800b9868 820b6d94 00000189 820b72e0 80238b12
 7fff7ba8 00000022 00000000 8028a23c 80287cdc 80239200 802391bc 802391bc
 80239200 80287cdc 00000014 00000005 800da9e4 80238af0 19669944 83feb000
 8028a9d4 00000202 00000000 0000000b 7fff7ba8 00000000 00000001 00008400
 820b1ea0 00000000 00000002 8028a9d4 00000003 820e9ef8 00000002 00000000
 7fff7ba8 0000000b 00000000 7fff7a28 7fff7d48 00000004 00000014 00000000
 2ab61a30 00000000 00000000 2abe7bf0 7fff79b8 00000005 0040709c 00000000
 00000000 2ab61a94 00000008 00008413 10800020 fbbffffe fb7fefff ffffdffb
 bbefefef fdf67ffe b6e5efbd f7f7fff6 efedffff
show_trace =============================================================


Call Trace:
[<800b93cc>__call_console_drivers ]
[<80111bb0>do_select]
[<800b9460> _call_console_drivers ]
[<800b9ac0>release_console_sem]
[<800b99bc>release_console_sem]

[<80239200>] [<802391bc>] [<80239200>] [<800b9868>] [<80238b12>] [<80239200>]
 [<802391bc>] [<802391bc>] [<80239200>] [<800da9e4>] [<80238af0>]
show_code ==============================================================

Code:<7>init: Forwarding exception at [<800acfe0>] (80256a18)
 (Bad address in epc)

Kernel panic: Attempted to kill init!
 UART_MSR_ANY_DELTA




===================================Error Output End ======================


From the error messages, it seems that the function named
"__call_console_drivers() has problem.
I know, printk() will call release_console_sem to call
__call_console_drivers() to call specify serial driver to output
kernel output.

I found when resume,  __call_console_drivers didn't call specified
serial driver successfully.
When suspend:
first, it can call serial driver(I added debugging info in serial driver).
but after processes frozen, serial driver messages can't be printed
out, but printk work well.
for example , printk("my name is bob \n"); can output to console
successfully, but serial driver messages can't be printed out.


what I tried:

1, because i only have serial console. so I feel that , I don't need
"CONFIG_VT" AND CONFIG_VT_CONSOLE.
I have selected CONFIG_SERIAL AND CONFIG_SERIAL_CONSOLE.

The problem still exist.


2, I have implemented save cpu context and restore cpu context.
//char __nosavedata swsusp_pg_dir[PAGE_SIZE] __attribute__ ((aligned
(PAGE_SIZE)));

/* image of the saved processor states
 * Based on MIPS registers ,refine it , bob
 */
struct saved_context {
       u32     zero;      /* wired zero */
       u32     AT;      /* assembler temp  - uppercase because of ".set at" */
       u32 v0  ;         /* return value */
       u32  v1  ;
       u32  a0  ;         /* argument registers */
       u32  a1  ;
       u32  a2 ;
       u32  a3   ;
       u32  t0    ;        /* caller saved */
       u32  t1   ;
       u32  t2   ;
       u32  t3   ;
       u32  t4   ;
       u32  t5  ;
       u32  t6   ;
       u32  t7    ;
       u32  s0   ;       /* callee saved */
       u32  s1   ;
       u32  s2   ;
       u32  s3   ;
       u32  s4  ;
       u32  s5    ;
       u32  s6   ;
       u32  s7   ;
       u32  t8   ;       /* caller saved */
       u32  t9   ;
       u32  jp   ;        /* PIC jump register */
       u32  k0  ;        /* kernel scratch */
       u32  k1  ;
       u32  gp  ;         /* global pointer */
       u32  sp  ;        /* stack pointer */
       u32  fp  ;         /* frame pointer */
       u32  s8 ;       /* same like fp! */
       u32  ra  ;         /* return address */

       /* special registers */
       u32 hi;
       u32 lo;

       /* cp0 */
       u32 cp0[32];

};

struct saved_context saved_contexts[NR_CPUS];
struct saved_context saved_context;     /* temporary storage */


static inline void save_processor_context(void)
{
       //bob
       //kernel_fpu_begin();

//      asm volatile (".set     noreorder");
       /* save all 32 registers of MIPS */

       //only debug,  I am not sure ,bob
       //I didn't save $0 , it is useless for us,because it is always 0 ,
like /dev/null
       asm volatile ("sw $1,   (%0)"  : "=m" (saved_context.AT));
       asm volatile ("sw $2,   (%0)"  : "=m" (saved_context.v0));
       asm volatile ("sw $3,   (%0)"  : "=m" (saved_context.v1));
       asm volatile ("sw $4,   (%0)"  : "=m" (saved_context.a0));
       asm volatile ("sw $5,   (%0)"  : "=m" (saved_context.a1));
       asm volatile ("sw $6,   (%0)"  : "=m" (saved_context.a2));
       asm volatile ("sw $7,   (%0)"  : "=m" (saved_context.a3));
       asm volatile ("sw $8,   (%0)"  : "=m" (saved_context.t0));
       asm volatile ("sw $9,   (%0)"  : "=m" (saved_context.t1));
       asm volatile ("sw $10,  (%0)"  : "=m" (saved_context.t2));
       asm volatile ("sw $11,  (%0)"  : "=m" (saved_context.t3));
       asm volatile ("sw $12,  (%0)"  : "=m" (saved_context.t4));
       asm volatile ("sw $13,  (%0)"  : "=m" (saved_context.t5));
       asm volatile ("sw $14,  (%0)"  : "=m" (saved_context.t6));
       asm volatile ("sw $15,  (%0)"  : "=m" (saved_context.t7));
       asm volatile ("sw $16,  (%0)"  : "=m" (saved_context.s0));
       asm volatile ("sw $17,  (%0)"  : "=m" (saved_context.s1));
       asm volatile ("sw $18,  (%0)"  : "=m" (saved_context.s2));
       asm volatile ("sw $19,  (%0)"  : "=m" (saved_context.s3));
       asm volatile ("sw $20,  (%0)"  : "=m" (saved_context.s4));
       asm volatile ("sw $21,  (%0)"  : "=m" (saved_context.s5));
       asm volatile ("sw $22,  (%0)"  : "=m" (saved_context.s6));
       asm volatile ("sw $23,  (%0)"  : "=m" (saved_context.s7));
       asm volatile ("sw $24,  (%0)"  : "=m" (saved_context.t8));

       asm volatile ("sw $25,  (%0)"  : "=m" (saved_context.t9));  //jp and t9
       asm volatile ("sw $25,  (%0)"  : "=m" (saved_context.jp));  //jp and t9

       asm volatile ("sw $26,  (%0)"  : "=m" (saved_context.k0));
       asm volatile ("sw $27,  (%0)"  : "=m" (saved_context.k1));
       asm volatile ("sw $28,  (%0)"  : "=m" (saved_context.gp));
       asm volatile ("sw $29,  (%0)"  : "=m" (saved_context.sp));

       asm volatile ("sw $30,  (%0)"  : "=m" (saved_context.fp));// fp and s8
       asm volatile ("sw $30,  (%0)"  : "=m" (saved_context.s8));  //jp and t9
       asm volatile ("sw $31,  (%0)"  : "=m" (saved_context.ra));




       /*
        * special registers
        */
       asm volatile ("mfhi %0" : "=r" (saved_context.hi));
       asm volatile ("mflo %0" : "=r" (saved_context.lo));
       // load/link register??

       /*
        * coprocessor 0 registers (inclde/asm-mips/mipsregs.h)
        */
       asm volatile ("mfc0 %0, $0" : "=r" (saved_context.cp0[0]));
       asm volatile ("mfc0 %0, $1" : "=r" (saved_context.cp0[1]));
       asm volatile ("mfc0 %0, $2" : "=r" (saved_context.cp0[2]));
       asm volatile ("mfc0 %0, $3" : "=r" (saved_context.cp0[3]));
       asm volatile ("mfc0 %0, $4" : "=r" (saved_context.cp0[4]));
       asm volatile ("mfc0 %0, $5" : "=r" (saved_context.cp0[5]));
       asm volatile ("mfc0 %0, $6" : "=r" (saved_context.cp0[6]));
       asm volatile ("mfc0 %0, $7" : "=r" (saved_context.cp0[7]));
       asm volatile ("mfc0 %0, $8" : "=r" (saved_context.cp0[8]));
       asm volatile ("mfc0 %0, $9" : "=r" (saved_context.cp0[9]));
       asm volatile ("mfc0 %0, $10" : "=r" (saved_context.cp0[10]));
       asm volatile ("mfc0 %0, $11" : "=r" (saved_context.cp0[11]));
       asm volatile ("mfc0 %0, $12" : "=r" (saved_context.cp0[12]));
       asm volatile ("mfc0 %0, $13" : "=r" (saved_context.cp0[13]));
       asm volatile ("mfc0 %0, $14" : "=r" (saved_context.cp0[14]));  //EPC
       asm volatile ("mfc0 %0, $15" : "=r" (saved_context.cp0[15]));
       asm volatile ("mfc0 %0, $16" : "=r" (saved_context.cp0[16]));
       asm volatile ("mfc0 %0, $17" : "=r" (saved_context.cp0[17]));
       asm volatile ("mfc0 %0, $18" : "=r" (saved_context.cp0[18]));
       asm volatile ("mfc0 %0, $19" : "=r" (saved_context.cp0[19]));
       asm volatile ("mfc0 %0, $20" : "=r" (saved_context.cp0[20]));
       asm volatile ("mfc0 %0, $21" : "=r" (saved_context.cp0[21]));
       asm volatile ("mfc0 %0, $22" : "=r" (saved_context.cp0[22]));
       asm volatile ("mfc0 %0, $23" : "=r" (saved_context.cp0[23]));
       asm volatile ("mfc0 %0, $24" : "=r" (saved_context.cp0[24]));
       asm volatile ("mfc0 %0, $25" : "=r" (saved_context.cp0[25]));
       asm volatile ("mfc0 %0, $26" : "=r" (saved_context.cp0[26]));
       asm volatile ("mfc0 %0, $27" : "=r" (saved_context.cp0[27]));
       asm volatile ("mfc0 %0, $28" : "=r" (saved_context.cp0[28]));
       asm volatile ("mfc0 %0, $29" : "=r" (saved_context.cp0[29]));
       asm volatile ("mfc0 %0, $30" : "=r" (saved_context.cp0[30]));
       asm volatile ("mfc0 %0, $31" : "=r" (saved_context.cp0[31]));


}


static inline void restore_processor_context(void)
{
//      asm volatile (".set     noreorder");
       asm volatile (".align 4");

       /*
        * coprocessor 0 registers
        */
       asm volatile ("mtc0 %0, $0" : : "r" (saved_context.cp0[0]));
       asm volatile ("mtc0 %0, $1" : : "r" (saved_context.cp0[1]));
       asm volatile ("mtc0 %0, $2" : : "r" (saved_context.cp0[2]));
       asm volatile ("mtc0 %0, $3" : : "r" (saved_context.cp0[3]));
       asm volatile ("mtc0 %0, $4" : : "r" (saved_context.cp0[4]));
       asm volatile ("mtc0 %0, $5" : : "r" (saved_context.cp0[5]));
       asm volatile ("mtc0 %0, $6" : : "r" (saved_context.cp0[6]));
       asm volatile ("mtc0 %0, $7" : : "r" (saved_context.cp0[7]));
       asm volatile ("mtc0 %0, $8" : : "r" (saved_context.cp0[8]));
       asm volatile ("mtc0 %0, $9" : : "r" (saved_context.cp0[9]));
       asm volatile ("mtc0 %0, $10" : : "r" (saved_context.cp0[10]));
       asm volatile ("mtc0 %0, $11" : : "r" (saved_context.cp0[11]));
       asm volatile ("mtc0 %0, $12" : : "r" (saved_context.cp0[12]));
       asm volatile ("mtc0 %0, $13" : : "r" (saved_context.cp0[13]));
       asm volatile ("mtc0 %0, $14" : : "r" (saved_context.cp0[14]));  //epc
       asm volatile ("mtc0 %0, $15" : : "r" (saved_context.cp0[15]));
       asm volatile ("mtc0 %0, $16" : : "r" (saved_context.cp0[16]));
       asm volatile ("mtc0 %0, $17" : : "r" (saved_context.cp0[17]));
       asm volatile ("mtc0 %0, $18" : : "r" (saved_context.cp0[18]));
       asm volatile ("mtc0 %0, $19" : : "r" (saved_context.cp0[19]));
       asm volatile ("mtc0 %0, $20" : : "r" (saved_context.cp0[20]));
       asm volatile ("mtc0 %0, $21" : : "r" (saved_context.cp0[21]));
       asm volatile ("mtc0 %0, $22" : : "r" (saved_context.cp0[22]));
       asm volatile ("mtc0 %0, $23" : : "r" (saved_context.cp0[23]));
       asm volatile ("mtc0 %0, $24" : : "r" (saved_context.cp0[24]));
       asm volatile ("mtc0 %0, $25" : : "r" (saved_context.cp0[25]));
       asm volatile ("mtc0 %0, $26" : : "r" (saved_context.cp0[26]));
       asm volatile ("mtc0 %0, $27" : : "r" (saved_context.cp0[27]));
       asm volatile ("mtc0 %0, $28" : : "r" (saved_context.cp0[28]));
       asm volatile ("mtc0 %0, $29" : : "r" (saved_context.cp0[29]));
       asm volatile ("mtc0 %0, $30" : : "r" (saved_context.cp0[30]));
       asm volatile ("mtc0 %0, $31" : : "r" (saved_context.cp0[31]));

       /*
        * special registers
        */
       asm volatile ("mthi %0" : : "r" (saved_context.hi));
       asm volatile ("mtlo %0" : : "r" (saved_context.lo));



       asm volatile ("lw $1,(%0)"   :: "r" (&saved_context.AT));
       asm volatile ("lw $2,(%0)"   :: "r" (&saved_context.v0));
       asm volatile ("lw $3,(%0)"   :: "r" (&saved_context.v1));
       asm volatile ("lw $4,(%0)"   :: "r" (&saved_context.a0));
       asm volatile ("lw $5,(%0)"   :: "r" (&saved_context.a1));
       asm volatile ("lw $6,(%0)"   :: "r" (&saved_context.a2));
       asm volatile ("lw $7,(%0)"   :: "r" (&saved_context.a3));
       asm volatile ("lw $8,(%0)"   :: "r" (&saved_context.t0));
       asm volatile ("lw $9,(%0)"   :: "r" (&saved_context.t1));
       asm volatile ("lw $10,(%0)"  :: "r" (&saved_context.t2));
       asm volatile ("lw $11,(%0)"  :: "r" (&saved_context.t3));
       asm volatile ("lw $12,(%0)"  :: "r" (&saved_context.t4));
       asm volatile ("lw $13,(%0)"  :: "r" (&saved_context.t5));
       asm volatile ("lw $14,(%0)"  :: "r" (&saved_context.t6));
       asm volatile ("lw $15,(%0)"  :: "r" (&saved_context.t7));
       asm volatile ("lw $16,(%0)"  :: "r" (&saved_context.s0));
       asm volatile ("lw $17,(%0)"  :: "r" (&saved_context.s1));
       asm volatile ("lw $18,(%0)"  :: "r" (&saved_context.s2));
       asm volatile ("lw $19,(%0)"  :: "r" (&saved_context.s3));
       asm volatile ("lw $20,(%0)"  :: "r" (&saved_context.s4));
       asm volatile ("lw $21,(%0)"  :: "r" (&saved_context.s5));
       asm volatile ("lw $22,(%0)"  :: "r" (&saved_context.s6));
       asm volatile ("lw $23,(%0)"  :: "r" (&saved_context.s7));
       asm volatile ("lw $24,(%0)"  :: "r" (&saved_context.t8));

       asm volatile ("lw $25,(%0)"  :: "r" (&saved_context.t9));  //jp and t9
//      asm volatile ("lw $25,(%0)"  :: "r" (&saved_context.jp));  //jp and t9

       asm volatile ("lw $26,(%0)"  :: "r" (&saved_context.k0));
       asm volatile ("lw $27,(%0)"  :: "r" (&saved_context.k1));
       asm volatile ("lw $28,(%0)"  :: "r" (&saved_context.gp));
       asm volatile ("lw $29,(%0)"  :: "r" (&saved_context.sp));

       asm volatile ("lw $30,(%0)"  :: "r" (&saved_context.fp));// fp and s8
//      asm volatile ("lw $30,(%0)"  :: "r" (&saved_context.s8));  //jp and t9
       asm volatile ("lw $31,(%0)"  :: "r" (&saved_context.ra));

       //do_fpu_end();
}



3,  complete resume booting info and error messages:

*call = 80274ef8
Linux video capture interface: v1.00
*call = 80275708
*call = 80276430
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 4096 bind 4096)
*call = 802767f0
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
initcalls done
initcalls done2
basic setup 4
at start of software_resume2Calling dump_stack() ,
file(swsusp2.c),function(software_resume2),line(1245)
This architecture does not implement dump_stack()
Looking for first block of swap header at block 0.
Setting logical block size of resume device to 4096.
Software Suspend 2.0: Attempting to set blocksize for 302 to 4096.
wait_on_one_page(io_info);
enter wait_on_on_page() ,io_info address=821f0000
will sync
sync_swap_partitions over
into do_suspend_sync()
Software Suspend 2.0: Swap space signature found.
now in function :attempt_to_parse_resume_device
now software_suspend_state = 0
will into swsusp_init_proc() , line:1265 , file:swsusp2.c
numfiles=13
Software Suspend 2.0: Checking for image...
when about to read primary image
Calling dump_stack() , file(swsusp2.c),function(software_resume2),line(1287)
This architecture does not implement dump_stack()
at entrance to __read_primary_suspend_image
wait_on_one_page(io_info);
enter wait_on_on_page() ,io_info address=821f004c
will sync
sync_swap_partitions over
into do_suspend_sync()
after checking whether image exists
before preparing to read header
wait_on_one_page(io_info);
enter wait_on_on_page() ,io_info address=821f0098
will sync
sync_swap_partitions over
into do_suspend_sync()
before preparing to read suspend header
before doing sanity check
has into pm_prepare_console
About to read pagedir.
Reading 2 range pages.
Reading range page 0 [821dc000].
wait_on_one_page(io_info);
enter wait_on_on_page() ,io_info address=821f00e4
will sync
sync_swap_partitions over
into do_suspend_sync()
Reading range page 1 [821db000].
wait_on_one_page(io_info);
enter wait_on_on_page() ,io_info address=821f0130
will sync
sync_swap_partitions over
into do_suspend_sync()
Pagedir_resume.pageset_size is 5903

Allocating memory.
pagedir_resume.pageset_size=5903
Check_pagedir: Prepared 5903 of 5903 pages.
Pagedir prepared. About to read pageset 1.
at start of read pageset
Reading kernel & process data...

finish_at=5903
 23/32 MB |
Finish I/O, flush data and cleanup reads.
statistics
Time to read data: 5903 pages in 297 jiffies => MB read per second: 7.
at end of read pageset

after loading image.
About to restore original kernel.
Calling dump_stack() , file(swsusp2.c),function(software_resume2),line(1292)
This architecture does not implement dump_stack()
Calling dump_stack() , file(swsusp2.c),function(software_resume2),line(1307)
This architecture does not implement dump_stack()
process(ksoftirqd_CPU0) (3) is a syncthread at entrance to fridge
process(mtdblockd) (7) is a syncthread at entrance to fridge
process(khubd) (8) is a syncthread at entrance to fridge
into do_suspend_sync()
before FREEZE_UNREFRIGERATED , swsusp_state=1
begin to freeze remaining processes
Signalling.
keventd thread 2
we try to wake up process(keventd) ,pid(2) , its state is 1
,ksoftirqd_CPU0 thread 3
we try to wake up process(ksoftirqd_CPU0) ,pid(3) , its state is 1
,kswapd thread 4
we try to wake up process(kswapd) ,pid(4) , its state is 1
,bdflush thread 5
we try to wake up process(bdflush) ,pid(5) , its state is 1
,kupdated thread 6
we try to wake up process(kupdated) ,pid(6) , its state is 0
,mtdblockd thread 7
we try to wake up process(mtdblockd) ,pid(7) , its state is 1
,khubd thread 8
we try to wake up process(khubd) ,pid(8) , its state is 1
numsignalled=7
Schedule.
kupdated (6) refrigerated and sigpending recalculated.
kupdated (6) refrigerated.
keventd (2) refrigerated and sigpending recalculated.
keventd (2) refrigerated.
kswapd (4) refrigerated and sigpending recalculated.
kswapd (4) refrigerated.
bdflush (5) refrigerated and sigpending recalculated.
bdflush (5) refrigerated.
mtdblockd (7) refrigerated and sigpending recalculated.
mtdblockd (7) refrigerated.
khubd (8) refrigerated and sigpending recalculated.
khubd (8) refrigerated.
ksoftirqd_CPU0 (3) refrigerated and sigpending recalculated.
ksoftirqd_CPU0 (3) refrigerated.
Examine effect.
 newtodo = 0
Waiting on:
Calling dump_stack() , file(swsusp2.c),function(software_resume2),line(1312)
This architecture does not implement dump_stack()
Copying original kernel back (no status - sensitive!)...

Prior to calling do_swsusp_lowlevel.

before do_swsusp_lowlevel(1)
Calling dump_stack() , file(swsusp2.c),function(software_resume2),line(1327)
This architecture does not implement dump_stack()
swapper_pg_dir = 0x8027a000
Putting other CPUs in swsusp_lowevel in preparation for restoring contexts:

Done.
into do_suspend_sync()
host/usb-ohci.c: USB suspend: usb-00:00.0
ehci_hcd 00:01.0: suspend to state 3
Software Suspend 2.0: Waiting for DMAs to settle down...
Software Suspend 2.0: About to copy pageset1 back...
after do_swsusp_resume_1()
origoffset=0
copyoffset=768
max_low_pfn = 16384
min_low_pfn = 699
will restore_processor_context()
will flush_tlb_all()
will into do_swsusp2_resume_2()
In resume_2 after copy back.
will drivers_resume()
drivers_resume() will RESUME_PHASE2
About to reload secondary pagedir.
Beginning of read_secondary_pagedir:
at start of read pageset
Reading caches...

finish_at=2478
 9/9 MB |
Finish I/O, flush data and cleanup reads.
sync_swap_partitions over
into do_suspend_sync()
statistics
Time to read data: 2478 pages in 124 jiffies => MB read per second: 7.
at end of read pageset

Pagedir 2 read over .

Cleaning up...No Removing image for debugging easily
Removing image...
wait_on_one_page(io_info);
enter wait_on_on_page() ,io_info address=838c1000
will sync
sync_swap_partitions over
into do_suspend_sync()
wait_on_one_page(io_info);
enter wait_on_on_page() ,io_info address=838c104c
will sync
sync_swap_partitions over
into do_suspend_sync()
In resume_2 after fpu end.After unlocking irq_lock.
Resume drivers.
drivers_resume() will RESUME_PHASE2
Argh. Chip not in PM_SUSPENDED state upon resume()
PCI: Enabling bus mastering for device 00:00.0
host/usb-ohci.c: USB continue: usb-00:00.0 from host wakeup
ehci_hcd 00:01.0: resume
ok
At exit from save_image.
enable_swapfile
swapfilename=/dev/hda2
active swap partition result=0
Please include the following information in bug reports:
- SWSUSP core    : 2.0
- Kernel Version : 2.4.21-xfs
- Version spec.  : 2.0.0
- Compiler vers. : 2.91
- Modules loaded : emma_capcom demux vfat fat nfs lockd sunrpc dvbdev
venc emma_teletext emma_av emma_osd emma_bios emma_rtos zlib_deflate
- Attempt number : 1
- Pageset sizes  : 5903 and 2478 (2478 low).
- Parameters     : 0 2048 0 1 0 32
- Calculations   : Image size: 2489. Ram to suspend: 162.
- Limits         : 16384 pages RAM. Initial boot: 11232.
- Overall expected compression percentage: 0.
- Swapwriter active.
 Attempting to automatically swapon: /dev/hda2.
 Swap available for image: 0.
- Debugging compiled in.
- Max ranges used: 358 ranges in 2 pages.
Please include the following information in bug reports:
- SWSUSP core    : 2.0
- Kernel Version : 2.4.21-xfs
- Version spec.  : 2.0.0
- Compiler vers. : 2.91
- Modules loaded : emma_capcom demux vfat fat nfs lockd sunrpc dvbdev
venc emma_teletext emma_av emma_osd emma_bios emma_rtos zlib_deflate
- Attempt number : 1
- Pageset sizes  : 5903 and 2478 (2478 low).
- Parameters     : 0 2048 0 1 0 32
- Calculations   : Image size: 2489. Ram to suspend: 162.
- Limits         : 16384 pages RAM. Initial boot: 11232.
- Overall expected compression percentage: 0.
- Swapwriter active.
 Attempting to automatically swapon: /dev/hda2.
 Swap available for image: 0.
- Debugging compiled in.
- Max ranges used: 358 ranges in 2 pages.
will unsuspend IDE harddisk
free_pagedir(pagedir2)
free_pagedir(pagedir1)
wait_on_one_page(io_info);
enter wait_on_on_page() ,io_info address=838c1098
will sync
sync_swap_partitions over
into do_suspend_sync()
kstat_restore()
thaw_processes
Waking     1: init.
Waking     2: keventd.
Waking     3: ksoftirqd_CPU0.
Waking     4: kswapd.
Waking     5: bdflush.
Waking     6: kupdated.
Waking     7: mtdblockd.
Waking     8: khubd.
Waking    65: lircd.
Waking    67: inetd.
Waking    80: pure-ftpd.
Waking    81: sh.
Waking    86: hibernate.
Waking   163: hibernate.
Waking   164: tee.
About to restore original console.
swsusp_default_console_level = 1
console_loglevel=7
default_message_loglevel = 4
orig_default_message_loglevel=0
at end of do_software_suspend
Kernel unaligned instruction access in unaligned.c::do_ade, line 446:

CPU Regs : ===========================================================
$0 : 00000000 80290000 00000100 fffdffff 00000007 00000006 802342cc 820e83d4
$8 : 00000000 00000000 00000000 820e83dc 820e83f4 820e8000 80278010 00000000
$16: 8028f7b8 0000debe 00001ebe 802a53a0 0000dee0 7fff7d48 00000004 00000014
$24: 8200000c 2abe4090                   820e8000 820e9e70 00000000 0000000a
Hi : 0000007a
Lo : 000000b7
epc   : 0000000a    Tainted: G Z
Status: 10008403
Cause : 10800010
PrId  : 0001906c
Process init (pid: 1, stackpage=820e8000)
show_stack ============================================================
Stack:    80287ce0 0000003e 0000003c 800b93cc 00000000 00000400 80111bb0
 00000000 00001ee0 ffffffff 0000dee0 10008400 00000001 800b9460 0000000b
 00000189 00000004 00000001 10008400 802a4fc4 80287cf0 10008400 00000001
 0000000a 80287ce0 0000003c 800b9ac0 800b99bc 80239200 10008400 802391bc
 80239200 802a4fc2 802a4fc4 800b9868 820b6d94 00000189 820b72e0 80238b12
 7fff7ba8 00000022 00000000 8028a23c 80287cdc 80239200 802391bc 802391bc
 80239200 80287cdc 00000014 00000005 800da9e4 80238af0 19669944 83feb000
 8028a9d4 00000202 00000000 0000000b 7fff7ba8 00000000 00000001 00008400
 820b1ea0 00000000 00000002 8028a9d4 00000003 820e9ef8 00000002 00000000
 7fff7ba8 0000000b 00000000 7fff7a28 7fff7d48 00000004 00000014 00000000
 2ab61a30 00000000 00000000 2abe7bf0 7fff79b8 00000005 0040709c 00000000
 00000000 2ab61a94 00000008 00008413 10800020 fbbffffe fb7fefff ffffdffb
 bbefefef fdf67ffe b6e5efbd f7f7fff6 efedffff
show_trace =============================================================
Call Trace:   [<800b93cc>] [<80111bb0>] [<800b9460>] [<800b9ac0>] [<800b99bc>]
 [<80239200>] [<802391bc>] [<80239200>] [<800b9868>] [<80238b12>] [<80239200>]
 [<802391bc>] [<802391bc>] [<80239200>] [<800da9e4>] [<80238af0>]
show_code ==============================================================

Code:<7>init: Forwarding exception at [<800acfe0>] (80256a18)
 (Bad address in epc)

Kernel panic: Attempted to kill init!
 UART_MSR_ANY_DELTA
DSI_INIT!MMAC_CONFIG_InitialiseEMMAMMAC_CONFIG_InitialiseProcessor(main)
MMAC_CONFIG_InitRamVectors
DSI_INIT!
### MAIN PROCESSOR ### GENERAL EXCEPTION: Interrupt exception ###

Re: [PATCH 0/3] MIPS: Extend plat_* abstractions, cache support

[Bob Zhang]

Now , I have ported suspend2 code (based on 2.4.21 patch) into mips
architecture, my kernel version is 2.4.21.

My Environment:
kernel:2.4.21
Architecture:mips 32: 4KEc
tty device : only has a serial port.



Now, we have finish 99% work-load, but at last ,we found a problem,
kernel panic after resume code has been executed completely , kernel
code has return the code after hibernate. but system have not return
console, it happened kernel panic.

in resume code, I added debugging code, I am sure, resume code has
been executed completely.
including ,reading pageset1 and pageset2,and copy kernel to original
location, restore cpu context and unfroze processes.

Could you please give me some ideas and suggestions ? thanks very much!


----------
Error output is like this;

Waking     5: bdflush.
Waking     6: kupdated.
Waking     7: mtdblockd.
Waking     8: khubd.
Waking    65: lircd.
Waking    67: inetd.
Waking    80: pure-ftpd.
Waking    81: sh.
Waking    86: hibernate.
Waking   163: hibernate.
Waking   164: tee.
About to restore original console.
swsusp_default_console_level = 1
console_loglevel=7
default_message_loglevel = 4
orig_default_message_loglevel=0
at end of do_software_suspend
Kernel unaligned instruction access in unaligned.c::do_ade, line 446:

CPU Regs : ===========================================================
$0 : 00000000 80290000 00000100 fffdffff 00000007 00000006 802342cc 820e83d4
$8 : 00000000 00000000 00000000 820e83dc 820e83f4 820e8000 80278010 00000000
$16: 8028f7b8 0000debe 00001ebe 802a53a0 0000dee0 7fff7d48 00000004 00000014
$24: 8200000c 2abe4090                   820e8000 820e9e70 00000000 0000000a
Hi : 0000007a
Lo : 000000b7
epc   : 0000000a    Tainted: G Z
Status: 10008403
Cause : 10800010
PrId  : 0001906c
Process init (pid: 1, stackpage=820e8000)
show_stack ============================================================
Stack:    80287ce0 0000003e 0000003c 800b93cc 00000000 00000400 80111bb0
 00000000 00001ee0 ffffffff 0000dee0 10008400 00000001 800b9460 0000000b
 00000189 00000004 00000001 10008400 802a4fc4 80287cf0 10008400 00000001
 0000000a 80287ce0 0000003c 800b9ac0 800b99bc 80239200 10008400 802391bc
 80239200 802a4fc2 802a4fc4 800b9868 820b6d94 00000189 820b72e0 80238b12
 7fff7ba8 00000022 00000000 8028a23c 80287cdc 80239200 802391bc 802391bc
 80239200 80287cdc 00000014 00000005 800da9e4 80238af0 19669944 83feb000
 8028a9d4 00000202 00000000 0000000b 7fff7ba8 00000000 00000001 00008400
 820b1ea0 00000000 00000002 8028a9d4 00000003 820e9ef8 00000002 00000000
 7fff7ba8 0000000b 00000000 7fff7a28 7fff7d48 00000004 00000014 00000000
 2ab61a30 00000000 00000000 2abe7bf0 7fff79b8 00000005 0040709c 00000000
 00000000 2ab61a94 00000008 00008413 10800020 fbbffffe fb7fefff ffffdffb
 bbefefef fdf67ffe b6e5efbd f7f7fff6 efedffff
show_trace =============================================================


Call Trace:
[<800b93cc>__call_console_drivers ]
[<80111bb0>do_select]
[<800b9460> _call_console_drivers ]
[<800b9ac0>release_console_sem]
[<800b99bc>release_console_sem]

[<80239200>] [<802391bc>] [<80239200>] [<800b9868>] [<80238b12>] [<80239200>]
 [<802391bc>] [<802391bc>] [<80239200>] [<800da9e4>] [<80238af0>]
show_code ==============================================================

Code:<7>init: Forwarding exception at [<800acfe0>] (80256a18)
 (Bad address in epc)

Kernel panic: Attempted to kill init!
 UART_MSR_ANY_DELTA




===================================Error Output End ======================

Re: [PATCH 0/3] MIPS: Extend plat_* abstractions, cache support

[Ralf Baechle]

On Thu, Apr 23, 2009 at 05:03:43PM -0700, Kevin Cernekee wrote:

> I am upgrading an SoC to the 2.6.29.1 kernel from an earlier version,
> and in the process I am switching over the old board support
> customizations to use the newer, cleaner plat_* functions.  I found two
> cases where the plat_* functions did not provide enough information,
> so I had to modify the API:
> 
> plat_unmap_dma_mem() - Our handler needs to know the size and direction
> of the DMA mapping.  This information is not encoded in the DMA address,
> so it needed to be passed in explicitly.
> 
> plat_dma_addr_to_phys() - The bus<->physical address mappings differ
> based on which bus is being used.  It is not always possible to infer
> which bus is being used from the bus address alone, so I added a
> "struct device" to the function definition.
> 
> Also, our MIPS core uses 64-byte D$ lines, so I needed to generate the
> corresponding blast* functions.
> 
> These patches apply against the linux-mips.org GIT tree.

Queued for 2.6.31.  Thanks Kevin!

Which SoC port are you working on btw?

  Ralf