From: Raghu Gandham <raghu@mips.com>
To: linux-mips@linux-mips.org
Cc: chris@mips.com
Subject: [PATCH 01/15] Due to some broken bitfiles, we can't trust IntCtl
Date: Wed, 01 Jul 2009 19:39:54 -0700 [thread overview]
Message-ID: <20090702023954.23268.98988.stgit@linux-raghu> (raw)
In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu>
From: Robin Randhawa <robin@mips.com>
Signed-off-by: Chris Dearman <chris@mips.com>
---
arch/mips/include/asm/irq.h | 1 +
arch/mips/kernel/traps.c | 4 ++++
2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 09b08d0..ca0b5ed 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -158,6 +158,7 @@ extern void free_irqno(unsigned int irq);
* IE7. Since R2 their number has to be read from the c0_intctl register.
*/
#define CP0_LEGACY_COMPARE_IRQ 7
+#define CP0_LEGACY_PERFCNT_IRQ 7
extern int cp0_compare_irq;
extern int cp0_perfcount_irq;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 08f1edf..0b6e328 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1538,7 +1538,11 @@ void __cpuinit per_cpu_trap_init(void)
*/
if (cpu_has_mips_r2) {
cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
+ if (!cp0_compare_irq)
+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
+ if (!cp0_perfcount_irq)
+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
} else {
next prev parent reply other threads:[~2009-07-02 2:46 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-07-02 2:39 [PATCH 00/15] Port changes from linux-mti Raghu Gandham
2009-07-02 2:39 ` Raghu Gandham [this message]
2009-07-02 2:40 ` [PATCH 02/15] Fix absd emulation Raghu Gandham
2009-07-02 2:40 ` [PATCH 03/15] [MTI] Clean up SPRAM support a little Raghu Gandham
2009-07-02 2:40 ` [PATCH 04/15] Fix accesses to device registers on MIPS boards Raghu Gandham
2009-07-02 2:40 ` [PATCH 05/15] [MTI] MIPS secondary cache supports 64 byte line size Raghu Gandham
2009-07-02 2:41 ` [PATCH 06/15] [MTI] Enable PIIX4 PCI2.1 compliancy on Malta Raghu Gandham
2009-07-02 2:41 ` [PATCH 07/15] APRP Patch04: Propagate final value of max_low_pfn to max_pfn Raghu Gandham
2009-07-02 2:41 ` [PATCH 08/15] Fix compiler warning in vpe.c Raghu Gandham
2009-07-02 2:41 ` [PATCH 09/15] Add debug prints during CPU intialization Raghu Gandham
2009-07-02 2:42 ` [PATCH 10/15] Port of GIC related changes from MTI branch Raghu Gandham
2009-07-02 2:42 ` [PATCH 11/15] Add missing memory barriers for correct operation of amon_cpu_start Raghu Gandham
2009-07-02 2:42 ` [PATCH 12/15] Added coherentio command line option for DMA_NONCOHERENT kernel Raghu Gandham
2009-07-02 2:43 ` [PATCH 13/15] Avoid accessing GCMP registers when they are not present Raghu Gandham
2009-07-02 2:43 ` [PATCH 14/15] Avoid queing multiple reschedule IPI's in SMTC Raghu Gandham
2009-07-02 2:43 ` [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes Raghu Gandham
2009-07-02 4:02 ` Kevin D. Kissell
2009-07-02 21:46 ` Gandham, Raghu
2009-07-02 21:46 ` Gandham, Raghu
2009-07-02 22:08 ` Kevin D. Kissell
2009-10-12 16:17 ` Ralf Baechle
2009-10-12 20:20 ` [PATCH 15/15] Do not rely on the initial state of TC/VPEbindings " Gandham, Raghu
2009-10-12 20:20 ` Gandham, Raghu
2009-10-12 20:25 ` Ralf Baechle
2009-07-10 8:47 ` [PATCH 00/15] Port changes from linux-mti Gandham, Raghu
2009-07-10 8:47 ` Gandham, Raghu
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