* [PATCH] MIPS: Avoid destructive invalidation on partial L2 cachelines
@ 2009-09-19 2:12 Kevin Cernekee
2009-09-19 2:12 ` Kevin Cernekee
2009-09-23 22:20 ` Ralf Baechle
0 siblings, 2 replies; 3+ messages in thread
From: Kevin Cernekee @ 2009-09-19 2:12 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
the board cache code.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
arch/mips/mm/sc-mips.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index b55c2d1..5ab5fa8 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
*/
static void mips_sc_inv(unsigned long addr, unsigned long size)
{
+ unsigned long lsize = cpu_scache_line_size();
+ unsigned long almask = ~(lsize - 1);
+
+ cache_op(Hit_Writeback_Inv_SD, addr & almask);
+ cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
blast_inv_scache_range(addr, addr + size);
}
--
1.6.3.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] MIPS: Avoid destructive invalidation on partial L2 cachelines
2009-09-19 2:12 [PATCH] MIPS: Avoid destructive invalidation on partial L2 cachelines Kevin Cernekee
@ 2009-09-19 2:12 ` Kevin Cernekee
2009-09-23 22:20 ` Ralf Baechle
1 sibling, 0 replies; 3+ messages in thread
From: Kevin Cernekee @ 2009-09-19 2:12 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, linux-kernel
This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
the board cache code.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
arch/mips/mm/sc-mips.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index b55c2d1..5ab5fa8 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
*/
static void mips_sc_inv(unsigned long addr, unsigned long size)
{
+ unsigned long lsize = cpu_scache_line_size();
+ unsigned long almask = ~(lsize - 1);
+
+ cache_op(Hit_Writeback_Inv_SD, addr & almask);
+ cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
blast_inv_scache_range(addr, addr + size);
}
--
1.6.3.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] MIPS: Avoid destructive invalidation on partial L2 cachelines
2009-09-19 2:12 [PATCH] MIPS: Avoid destructive invalidation on partial L2 cachelines Kevin Cernekee
2009-09-19 2:12 ` Kevin Cernekee
@ 2009-09-23 22:20 ` Ralf Baechle
1 sibling, 0 replies; 3+ messages in thread
From: Ralf Baechle @ 2009-09-23 22:20 UTC (permalink / raw)
To: Kevin Cernekee; +Cc: linux-mips, linux-kernel
On Fri, Sep 18, 2009 at 07:12:45PM -0700, Kevin Cernekee wrote:
> This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
> the board cache code.
>
> Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Thanks Kevin, applied.
Ralf
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2009-09-23 22:19 UTC | newest]
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2009-09-19 2:12 ` Kevin Cernekee
2009-09-23 22:20 ` Ralf Baechle
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