[PATCH 00/15] Port changes from linux-mti

[PATCH 00/15] Port changes from linux-mti

[Raghu Gandham]

The following series of patches port the changes in linux-mti.git repository to the head of tree. 
---

Chris Dearman (9):
      Added coherentio command line option for DMA_NONCOHERENT kernel
      Add missing memory barriers for correct operation of amon_cpu_start
      Port of GIC related changes from MTI branch.
      Add debug prints during CPU intialization.
      APRP Patch04: Propagate final value of max_low_pfn to max_pfn
      [MTI] Enable PIIX4 PCI2.1 compliancy on Malta
      [MTI] MIPS secondary cache supports 64 byte line size.
      Fix accesses to device registers on MIPS boards
      [MTI] Clean up SPRAM support a little

Jaidev Patwardhan (2):
      Avoid queing multiple reschedule IPI's in SMTC
      Avoid accessing GCMP registers when they are not present

Kurt Martin (1):
      Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes

Raghu Gandham (1):
      Fix compiler warning in vpe.c

Robin Randhawa (2):
      Fix absd emulation
      Due to some broken bitfiles, we can't trust IntCtl


 arch/mips/Kconfig                 |    1 
 arch/mips/include/asm/gcmpregs.h  |   18 ++--
 arch/mips/include/asm/gic.h       |  188 ++++---------------------------------
 arch/mips/include/asm/irq.h       |    1 
 arch/mips/include/asm/smtc_ipi.h  |    5 +
 arch/mips/include/asm/spram.h     |   10 ++
 arch/mips/kernel/cpu-probe.c      |    8 --
 arch/mips/kernel/irq-gic.c        |  116 +++++++++--------------
 arch/mips/kernel/setup.c          |    3 -
 arch/mips/kernel/smp-mt.c         |   10 ++
 arch/mips/kernel/smtc.c           |   45 ++++++++-
 arch/mips/kernel/spram.c          |    5 -
 arch/mips/kernel/traps.c          |    4 +
 arch/mips/kernel/vpe.c            |    3 -
 arch/mips/math-emu/dp_simple.c    |   11 +-
 arch/mips/math-emu/sp_simple.c    |    3 -
 arch/mips/mti-malta/malta-amon.c  |    7 +
 arch/mips/mti-malta/malta-int.c   |  115 ++++++++++++++---------
 arch/mips/mti-malta/malta-pci.c   |   14 ++-
 arch/mips/mti-malta/malta-setup.c |  111 ++++++++++++++++++++++
 20 files changed, 351 insertions(+), 327 deletions(-)
 create mode 100644 arch/mips/include/asm/spram.h

[PATCH 01/15] Due to some broken bitfiles, we can't trust IntCtl

[Raghu Gandham]

From: Robin Randhawa <robin@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/include/asm/irq.h |    1 +
 arch/mips/kernel/traps.c    |    4 ++++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 09b08d0..ca0b5ed 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -158,6 +158,7 @@ extern void free_irqno(unsigned int irq);
  * IE7.  Since R2 their number has to be read from the c0_intctl register.
  */
 #define CP0_LEGACY_COMPARE_IRQ 7
+#define CP0_LEGACY_PERFCNT_IRQ 7
 
 extern int cp0_compare_irq;
 extern int cp0_perfcount_irq;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 08f1edf..0b6e328 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1538,7 +1538,11 @@ void __cpuinit per_cpu_trap_init(void)
 	 */
 	if (cpu_has_mips_r2) {
 		cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
+		if (!cp0_compare_irq)
+			cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
 		cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
+		if (!cp0_perfcount_irq)
+			cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
 		if (cp0_perfcount_irq == cp0_compare_irq)
 			cp0_perfcount_irq = -1;
 	} else {

[PATCH 02/15] Fix absd emulation

[Raghu Gandham]

From: Robin Randhawa <robin@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/math-emu/dp_simple.c |   11 ++++-------
 arch/mips/math-emu/sp_simple.c |    3 ---
 2 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c
index 1c555e6..6ff4655 100644
--- a/arch/mips/math-emu/dp_simple.c
+++ b/arch/mips/math-emu/dp_simple.c
@@ -76,15 +76,12 @@ ieee754dp ieee754dp_abs(ieee754dp x)
 	CLEARCX;
 	FLUSHXDP;
 
+	/* Clear sign ALWAYS, irrespective of NaN */
+	DPSIGN(x) = 0;
+
 	if (xc == IEEE754_CLASS_SNAN) {
 		SETCX(IEEE754_INVALID_OPERATION);
-		return ieee754dp_nanxcpt(ieee754dp_indef(), "neg");
+		return ieee754dp_nanxcpt(ieee754dp_indef(), "abs");
 	}
-
-	if (ieee754dp_isnan(x))	/* but not infinity */
-		return ieee754dp_nanxcpt(x, "abs", x);
-
-	/* quick fix up */
-	DPSIGN(x) = 0;
 	return x;
 }
diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c
index 770f0f4..cdec1a2 100644
--- a/arch/mips/math-emu/sp_simple.c
+++ b/arch/mips/math-emu/sp_simple.c
@@ -61,9 +61,6 @@ ieee754sp ieee754sp_neg(ieee754sp x)
 		SPSIGN(y) = SPSIGN(x);
 		return ieee754sp_nanxcpt(y, "neg");
 	}
-
-	if (ieee754sp_isnan(x))	/* but not infinity */
-		return ieee754sp_nanxcpt(x, "neg", x);
 	return x;
 }
 

[PATCH 03/15] [MTI] Clean up SPRAM support a little

[Raghu Gandham]

From: Chris Dearman <chris@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/include/asm/spram.h |   10 ++++++++++
 arch/mips/kernel/cpu-probe.c  |    8 +-------
 arch/mips/kernel/spram.c      |    5 ++---
 3 files changed, 13 insertions(+), 10 deletions(-)
 create mode 100644 arch/mips/include/asm/spram.h

diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h
new file mode 100644
index 0000000..0b89006
--- /dev/null
+++ b/arch/mips/include/asm/spram.h
@@ -0,0 +1,10 @@
+#ifndef _MIPS_SPRAM_H
+#define _MIPS_SPRAM_H
+
+#ifdef CONFIG_CPU_MIPSR2
+extern __init void spram_config(void);
+#else
+static inline void spram_config(void) { };
+#endif /* CONFIG_CPU_MIPSR2 */
+
+#endif /* _MIPS_SPRAM_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1abe990..2d35217 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -23,7 +23,7 @@
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 #include <asm/watch.h>
-
+#include <asm/spram.h>
 /*
  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  * the implementation of the "wait" feature differs between CPU families. This
@@ -711,12 +711,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 	mips_probe_watch_registers(c);
 }
 
-#ifdef CONFIG_CPU_MIPSR2
-extern void spram_config(void);
-#else
-static inline void spram_config(void) {}
-#endif
-
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 6ddb507..1821d12 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -13,7 +13,6 @@
 #include <linux/ptrace.h>
 #include <linux/stddef.h>
 
-#include <asm/cpu.h>
 #include <asm/fpu.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
@@ -198,8 +197,7 @@ static __cpuinit void probe_spram(char *type,
 		offset += 2 * SPRAM_TAG_STRIDE;
 	}
 }
-
-__cpuinit void spram_config(void)
+void __cpuinit spram_config(void)
 {
 	struct cpuinfo_mips *c = &current_cpu_data;
 	unsigned int config0;
@@ -208,6 +206,7 @@ __cpuinit void spram_config(void)
 	case CPU_24K:
 	case CPU_34K:
 	case CPU_74K:
+	case CPU_1004K:
 		config0 = read_c0_config();
 		/* FIXME: addresses are Malta specific */
 		if (config0 & (1<<24)) {

[PATCH 04/15] Fix accesses to device registers on MIPS boards

[Raghu Gandham]

From: Chris Dearman <chris@mips.com>

This fixes the remaining problems introduced by
f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length &
byteswapping in bigendian mode)

Signed-off-by: Chris Dearman (chris@mips.com)
---

 arch/mips/mti-malta/malta-int.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index a8756f8..e9ba8b3 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void)
 		dummy = BONITO_PCIMAP_CFG;
 		iob();    /* sync */
 
-		irq = readl((u32 *)_pcictrl_bonito_pcicfg);
+		irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
 		iob();    /* sync */
 		irq &= 0xff;
 		BONITO_PCIMAP_CFG = 0;

[PATCH 05/15] [MTI] MIPS secondary cache supports 64 byte line size.

[Raghu Gandham]

From: Chris Dearman <chris@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index df1a92a..60c7235 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1012,6 +1012,7 @@ config MIPS_L1_CACHE_SHIFT
 	int
 	default "4" if MACH_DECSTATION || MIKROTIK_RB532
 	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
+	default "6" if MIPS_CPU_SCACHE
 	default "4" if PMC_MSP4200_EVAL
 	default "5"
 

[PATCH 06/15] [MTI] Enable PIIX4 PCI2.1 compliancy on Malta

[Raghu Gandham]

From: Chris Dearman <chris@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/mti-malta/malta-setup.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index dc78b89..69f5f9c 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -223,3 +223,14 @@ void __init plat_mem_setup(void)
 	board_be_init = malta_be_init;
 	board_be_handler = malta_be_handler;
 }
+/* Enable PCI 2.1 compatibility in PIIX4 */
+static void __init quirk_dlcsetup(struct pci_dev *dev)
+{
+	u8 odlc, ndlc;
+	(void) pci_read_config_byte(dev, 0x82, &odlc);
+	/* Enable passive releases and delayed transaction */
+	ndlc = odlc | 7;
+	(void) pci_write_config_byte(dev, 0x82, ndlc);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
+		quirk_dlcsetup);

[PATCH 07/15] APRP Patch04: Propagate final value of max_low_pfn to max_pfn

[Raghu Gandham]

From: Chris Dearman <chris@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/kernel/setup.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 2950b97..1e9862d 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -326,7 +326,6 @@ static void __init bootmem_init(void)
 	/*
 	 * Determine low and high memory ranges
 	 */
-	max_pfn = max_low_pfn;
 	if (max_low_pfn > PFN_DOWN(HIGHMEM_START)) {
 #ifdef CONFIG_HIGHMEM
 		highstart_pfn = PFN_DOWN(HIGHMEM_START);
@@ -334,6 +333,8 @@ static void __init bootmem_init(void)
 #endif
 		max_low_pfn = PFN_DOWN(HIGHMEM_START);
 	}
+	/* Propagate final value of max_low_pfn to max_pfn */
+	max_pfn = max_low_pfn;
 
 	/*
 	 * Initialize the boot-time allocator with low memory only.

[PATCH 08/15] Fix compiler warning in vpe.c

[Raghu Gandham]

Signed-off-by: Raghu Gandham (raghu@mips.com)
---

 arch/mips/kernel/vpe.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 07b9ec2..3d4ef84 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -327,7 +327,8 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,
 			    || (s->sh_flags & masks[m][1])
 			    || s->sh_entsize != ~0UL)
 				continue;
-			s->sh_entsize = get_offset(&mod->core_size, s);
+			s->sh_entsize =
+				get_offset((unsigned long *)&mod->core_size, s);
 		}
 
 		if (m == 0)

[PATCH 09/15] Add debug prints during CPU intialization.

[Raghu Gandham]

From: Chris Dearman <chris@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/kernel/smp-mt.c |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 6f7ee5a..c6c7b54 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -152,7 +152,7 @@ static void vsmp_send_ipi_mask(cpumask_t mask, unsigned int action)
 static void __cpuinit vsmp_init_secondary(void)
 {
 	extern int gic_present;
-
+	pr_debug("SMPMT: CPU%d: vsmp_init_secondary\n", smp_processor_id());
 	/* This is Malta specific: IPI,performance and timer inetrrupts */
 	if (gic_present)
 		change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
@@ -164,6 +164,8 @@ static void __cpuinit vsmp_init_secondary(void)
 
 static void __cpuinit vsmp_smp_finish(void)
 {
+	pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id());
+
 	/* CDFIXME: remove this? */
 	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
 
@@ -178,6 +180,7 @@ static void __cpuinit vsmp_smp_finish(void)
 
 static void vsmp_cpus_done(void)
 {
+	pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id());
 }
 
 /*
@@ -191,6 +194,8 @@ static void vsmp_cpus_done(void)
 static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
 {
 	struct thread_info *gp = task_thread_info(idle);
+	pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n",
+		smp_processor_id(), cpu);
 	dvpe();
 	set_c0_mvpcontrol(MVPCONTROL_VPC);
 
@@ -232,6 +237,7 @@ static void __init vsmp_smp_setup(void)
 	unsigned int mvpconf0, ntc, tc, ncpu = 0;
 	unsigned int nvpe;
 
+	pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id());
 #ifdef CONFIG_MIPS_MT_FPAFF
 	/* If we have an FPU, enroll ourselves in the FPU-full mask */
 	if (cpu_has_fpu)
@@ -272,6 +278,8 @@ static void __init vsmp_smp_setup(void)
 
 static void __init vsmp_prepare_cpus(unsigned int max_cpus)
 {
+	pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n",
+		smp_processor_id(), max_cpus);
 	mips_mt_set_cpuoptions();
 }
 

[PATCH 10/15] Port of GIC related changes from MTI branch.

[Raghu Gandham]

From: Chris Dearman <chris@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/include/asm/gcmpregs.h |   18 ++--
 arch/mips/include/asm/gic.h      |  188 ++++----------------------------------
 arch/mips/kernel/irq-gic.c       |  116 +++++++++--------------
 arch/mips/mti-malta/malta-int.c  |   97 ++++++++++++--------
 arch/mips/mti-malta/malta-pci.c  |   14 ++-
 5 files changed, 142 insertions(+), 291 deletions(-)

diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h
index 36fd969..c0cf76a 100644
--- a/arch/mips/include/asm/gcmpregs.h
+++ b/arch/mips/include/asm/gcmpregs.h
@@ -19,15 +19,20 @@
 #define GCMP_GDB_OFS		0x8000 /* Global Debug Block */
 
 /* Offsets to individual GCMP registers from GCMP base */
-#define GCMPOFS(block, tag, reg)	(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
+#define GCMPOFS(block, tag, reg)	\
+	(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
+#define GCMPOFSn(block, tag, reg, n) \
+	(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
 
 #define GCMPGCBOFS(reg)		GCMPOFS(GCB, GCB, reg)
+#define GCMPGCBOFSn(reg, n)	GCMPOFSn(GCB, GCB, reg, n)
 #define GCMPCLCBOFS(reg)	GCMPOFS(CLCB, CCB, reg)
 #define GCMPCOCBOFS(reg)	GCMPOFS(COCB, CCB, reg)
 #define GCMPGDBOFS(reg)		GCMPOFS(GDB, GDB, reg)
 
 /* GCMP register access */
 #define GCMPGCB(reg)			REGP(_gcmp_base, GCMPGCBOFS(reg))
+#define GCMPGCBn(reg, n)               REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
 #define GCMPCLCB(reg)			REGP(_gcmp_base, GCMPCLCBOFS(reg))
 #define GCMPCOCB(reg)			REGP(_gcmp_base, GCMPCOCBOFS(reg))
 #define GCMPGDB(reg)			REGP(_gcmp_base, GCMPGDBOFS(reg))
@@ -49,10 +54,10 @@
 #define  GCMP_GCB_GCMPB_GCMPBASE_MSK	GCMPGCBMSK(GCMPB_GCMPBASE, 17)
 #define  GCMP_GCB_GCMPB_CMDEFTGT_SHF	0
 #define  GCMP_GCB_GCMPB_CMDEFTGT_MSK	GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM	0
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM1	1
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
+#define  GCMP_GCB_GCMPB_CMDEFTGT_DISABLED	0
+#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM		1
+#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1		2
+#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2		3
 #define GCMP_GCB_CCMC_OFS		0x0010	/* Global CM Control */
 #define GCMP_GCB_GCSRAP_OFS		0x0020	/* Global CSR Access Privilege */
 #define  GCMP_GCB_GCSRAP_CMACCESS_SHF	0
@@ -115,5 +120,6 @@
 #define GCMP_CCB_DBGGROUP_OFS		0x0100		/* DebugBreak Group */
 
 extern int __init gcmp_probe(unsigned long, unsigned long);
-
+extern int __init gcmp_niocu(void);
+extern void __init gcmp_setregion(int, unsigned long, unsigned long, int);
 #endif /* _ASM_GCMPREGS_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 10292e3..9b9436a 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -12,7 +12,6 @@
 #define _ASM_GICREGS_H
 
 #undef	GICISBYTELITTLEENDIAN
-#define GICISWORDLITTLEENDIAN
 
 /* Constants */
 #define GIC_POL_POS			1
@@ -20,11 +19,7 @@
 #define GIC_TRIG_EDGE			1
 #define GIC_TRIG_LEVEL			0
 
-#if CONFIG_SMP
 #define GIC_NUM_INTRS			(24 + NR_CPUS * 2)
-#else
-#define GIC_NUM_INTRS			32
-#endif
 
 #define MSK(n) ((1 << (n)) - 1)
 #define REG32(addr)		(*(volatile unsigned int *) (addr))
@@ -70,13 +65,13 @@
 #define USM_VISIBLE_SECTION_SIZE	0x10000
 
 /* Register Map for Shared Section */
-#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
 
 #define	GIC_SH_CONFIG_OFS		0x0000
 
 /* Shared Global Counter */
 #define GIC_SH_COUNTER_31_00_OFS	0x0010
 #define GIC_SH_COUNTER_63_32_OFS	0x0014
+#define GIC_SH_REVISIONID_OFS		0x0020
 
 /* Interrupt Polarity */
 #define GIC_SH_POL_31_0_OFS		0x0100
@@ -164,24 +159,31 @@
 	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
 #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)	(1 << ((vpe) % 32))
 
+/* Convert an interrupt number to a byte offset/bit for multi-word registers */
+#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
+#define GIC_INTR_BIT(intr) ((intr) % 32)
+
 /* Polarity : Reset Value is always 0 */
 #define GIC_SH_SET_POLARITY_OFS		0x0100
 #define GIC_SET_POLARITY(intr, pol) \
-	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
+	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
+		GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
 
 /* Triggering : Reset Value is always 0 */
 #define GIC_SH_SET_TRIGGER_OFS		0x0180
 #define GIC_SET_TRIGGER(intr, trig) \
-	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
+	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
+		GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
 
 /* Mask manipulation */
 #define GIC_SH_SMASK_OFS		0x0380
-#define GIC_SET_INTR_MASK(intr, val) \
-	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
-
+#define GIC_SET_INTR_MASK(intr) \
+	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
+		GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
 #define GIC_SH_RMASK_OFS		0x0300
-#define GIC_CLR_INTR_MASK(intr, val) \
-	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
+#define GIC_CLR_INTR_MASK(intr) \
+	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
+		GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
 
 /* Register Map for Local Section */
 #define GIC_VPE_CTL_OFS			0x0000
@@ -219,161 +221,6 @@
 #define GIC_UMV_SH_COUNTER_31_00_OFS	0x0000
 #define GIC_UMV_SH_COUNTER_63_32_OFS	0x0004
 
-#else /* CONFIG_CPU_BIG_ENDIAN */
-
-#define	GIC_SH_CONFIG_OFS		0x0000
-
-/* Shared Global Counter */
-#define GIC_SH_COUNTER_31_00_OFS	0x0014
-#define GIC_SH_COUNTER_63_32_OFS	0x0010
-
-/* Interrupt Polarity */
-#define GIC_SH_POL_31_0_OFS		0x0104
-#define GIC_SH_POL_63_32_OFS		0x0100
-#define GIC_SH_POL_95_64_OFS		0x010c
-#define GIC_SH_POL_127_96_OFS		0x0108
-#define GIC_SH_POL_159_128_OFS		0x0114
-#define GIC_SH_POL_191_160_OFS		0x0110
-#define GIC_SH_POL_223_192_OFS		0x011c
-#define GIC_SH_POL_255_224_OFS		0x0118
-
-/* Edge/Level Triggering */
-#define GIC_SH_TRIG_31_0_OFS		0x0184
-#define GIC_SH_TRIG_63_32_OFS		0x0180
-#define GIC_SH_TRIG_95_64_OFS		0x018c
-#define GIC_SH_TRIG_127_96_OFS		0x0188
-#define GIC_SH_TRIG_159_128_OFS		0x0194
-#define GIC_SH_TRIG_191_160_OFS		0x0190
-#define GIC_SH_TRIG_223_192_OFS		0x019c
-#define GIC_SH_TRIG_255_224_OFS		0x0198
-
-/* Dual Edge Triggering */
-#define GIC_SH_DUAL_31_0_OFS		0x0204
-#define GIC_SH_DUAL_63_32_OFS		0x0200
-#define GIC_SH_DUAL_95_64_OFS		0x020c
-#define GIC_SH_DUAL_127_96_OFS		0x0208
-#define GIC_SH_DUAL_159_128_OFS		0x0214
-#define GIC_SH_DUAL_191_160_OFS		0x0210
-#define GIC_SH_DUAL_223_192_OFS		0x021c
-#define GIC_SH_DUAL_255_224_OFS		0x0218
-
-/* Set/Clear corresponding bit in Edge Detect Register */
-#define GIC_SH_WEDGE_OFS		0x0280
-
-/* Reset Mask - Disables Interrupt */
-#define GIC_SH_RMASK_31_0_OFS		0x0304
-#define GIC_SH_RMASK_63_32_OFS		0x0300
-#define GIC_SH_RMASK_95_64_OFS		0x030c
-#define GIC_SH_RMASK_127_96_OFS		0x0308
-#define GIC_SH_RMASK_159_128_OFS	0x0314
-#define GIC_SH_RMASK_191_160_OFS	0x0310
-#define GIC_SH_RMASK_223_192_OFS	0x031c
-#define GIC_SH_RMASK_255_224_OFS	0x0318
-
-/* Set Mask (WO) - Enables Interrupt */
-#define GIC_SH_SMASK_31_0_OFS		0x0384
-#define GIC_SH_SMASK_63_32_OFS		0x0380
-#define GIC_SH_SMASK_95_64_OFS		0x038c
-#define GIC_SH_SMASK_127_96_OFS		0x0388
-#define GIC_SH_SMASK_159_128_OFS	0x0394
-#define GIC_SH_SMASK_191_160_OFS	0x0390
-#define GIC_SH_SMASK_223_192_OFS	0x039c
-#define GIC_SH_SMASK_255_224_OFS	0x0398
-
-/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
-#define GIC_SH_MASK_31_0_OFS		0x0404
-#define GIC_SH_MASK_63_32_OFS		0x0400
-#define GIC_SH_MASK_95_64_OFS		0x040c
-#define GIC_SH_MASK_127_96_OFS		0x0408
-#define GIC_SH_MASK_159_128_OFS		0x0414
-#define GIC_SH_MASK_191_160_OFS		0x0410
-#define GIC_SH_MASK_223_192_OFS		0x041c
-#define GIC_SH_MASK_255_224_OFS		0x0418
-
-/* Pending Global Interrupts (RO) */
-#define GIC_SH_PEND_31_0_OFS		0x0484
-#define GIC_SH_PEND_63_32_OFS		0x0480
-#define GIC_SH_PEND_95_64_OFS		0x048c
-#define GIC_SH_PEND_127_96_OFS		0x0488
-#define GIC_SH_PEND_159_128_OFS		0x0494
-#define GIC_SH_PEND_191_160_OFS		0x0490
-#define GIC_SH_PEND_223_192_OFS		0x049c
-#define GIC_SH_PEND_255_224_OFS		0x0498
-
-#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS	0x0500
-
-/* Maps Interrupt X to a Pin */
-#define GIC_SH_MAP_TO_PIN(intr) \
-	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
-
-#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS	0x2004
-
-/*
- * Maps Interrupt X to a VPE.  This is more complex than the LE case, as
- * odd and even registers need to be transposed.  It does work - trust me!
- */
-#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
-	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
-	(((((vpe) / 32) ^ 1) - 1) * 4))
-#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)	(1 << ((vpe) % 32))
-
-/* Polarity */
-#define GIC_SH_SET_POLARITY_OFS		0x0100
-#define GIC_SET_POLARITY(intr, pol) \
-	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
-
-/* Triggering */
-#define GIC_SH_SET_TRIGGER_OFS		0x0180
-#define GIC_SET_TRIGGER(intr, trig) \
-	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
-
-/* Mask manipulation */
-#define GIC_SH_SMASK_OFS		0x0380
-#define GIC_SET_INTR_MASK(intr, val) \
-	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
-
-#define GIC_SH_RMASK_OFS		0x0300
-#define GIC_CLR_INTR_MASK(intr, val) \
-	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
-
-/* Register Map for Local Section */
-#define GIC_VPE_CTL_OFS			0x0000
-#define GIC_VPE_PEND_OFS		0x0004
-#define GIC_VPE_MASK_OFS		0x0008
-#define GIC_VPE_RMASK_OFS		0x000c
-#define GIC_VPE_SMASK_OFS		0x0010
-#define GIC_VPE_WD_MAP_OFS		0x0040
-#define GIC_VPE_COMPARE_MAP_OFS		0x0044
-#define GIC_VPE_TIMER_MAP_OFS		0x0048
-#define GIC_VPE_PERFCTR_MAP_OFS		0x0050
-#define GIC_VPE_SWINT0_MAP_OFS		0x0054
-#define GIC_VPE_SWINT1_MAP_OFS		0x0058
-#define GIC_VPE_OTHER_ADDR_OFS		0x0080
-#define GIC_VPE_WD_CONFIG0_OFS		0x0090
-#define GIC_VPE_WD_COUNT0_OFS		0x0094
-#define GIC_VPE_WD_INITIAL0_OFS		0x0098
-#define GIC_VPE_COMPARE_LO_OFS		0x00a4
-#define GIC_VPE_COMPARE_HI_OFS		0x00a0
-
-#define GIC_VPE_EIC_SHADOW_SET_BASE	0x0100
-#define GIC_VPE_EIC_SS(intr) \
-	(GIC_EIC_SHADOW_SET_BASE + (4 * intr))
-
-#define GIC_VPE_EIC_VEC_BASE		0x0800
-#define GIC_VPE_EIC_VEC(intr) \
-	(GIC_VPE_EIC_VEC_BASE + (4 * intr))
-
-#define GIC_VPE_TENABLE_NMI_OFS		0x1000
-#define GIC_VPE_TENABLE_YQ_OFS		0x1004
-#define GIC_VPE_TENABLE_INT_31_0_OFS	0x1080
-#define GIC_VPE_TENABLE_INT_63_32_OFS	0x1084
-
-/* User Mode Visible Section Register Map */
-#define GIC_UMV_SH_COUNTER_31_00_OFS	0x0004
-#define GIC_UMV_SH_COUNTER_63_32_OFS	0x0000
-
-#endif /* !LE */
-
 /* Masks */
 #define GIC_SH_CONFIG_COUNTSTOP_SHF	28
 #define GIC_SH_CONFIG_COUNTSTOP_MSK	(MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
@@ -473,12 +320,13 @@ struct gic_intrmask_regs {
  * in building ipi_map.
  */
 struct gic_intr_map {
-	unsigned int intrnum; 	/* Ext Intr Num 	*/
 	unsigned int cpunum;	/* Directed to this CPU */
 	unsigned int pin;	/* Directed to this Pin */
 	unsigned int polarity;	/* Polarity : +/-	*/
 	unsigned int trigtype;	/* Trigger  : Edge/Levl */
-	unsigned int ipiflag;	/* Is used for IPI ?	*/
+	unsigned int flags;	/* Misc flags	*/
+#define GIC_FLAG_IPI           0x01
+#define GIC_FLAG_TRANSPARENT   0x02
 };
 
 extern void gic_init(unsigned long gic_base_addr,
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index d2072cd..06d3506 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -14,38 +14,23 @@
 
 
 static unsigned long _gic_base;
-static unsigned int _irqbase, _mapsize, numvpes, numintrs;
-static struct gic_intr_map *_intrmap;
+static unsigned int _irqbase;
+static unsigned int gic_irq_flags[GIC_NUM_INTRS];
+#define GIC_IRQ_FLAG_EDGE      0x0001
 
-static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
+struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static struct gic_pending_regs pending_regs[NR_CPUS];
 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
 
-#define gic_wedgeb2bok 0	/*
-				 * Can GIC handle b2b writes to wedge register?
-				 */
-#if gic_wedgeb2bok == 0
-static DEFINE_SPINLOCK(gic_wedgeb2b_lock);
-#endif
-
 void gic_send_ipi(unsigned int intr)
 {
-#if gic_wedgeb2bok == 0
-	unsigned long flags;
-#endif
 	pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
 		 read_c0_status());
-	if (!gic_wedgeb2bok)
-		spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
 	GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
-	if (!gic_wedgeb2bok) {
-		(void) GIC_REG(SHARED, GIC_SH_CONFIG);
-		spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
-	}
 }
 
 /* This is Malta specific and needs to be exported */
-static void vpe_local_setup(unsigned int numvpes)
+static void __init vpe_local_setup(unsigned int numvpes)
 {
 	int i;
 	unsigned long timer_interrupt = 5, perf_interrupt = 5;
@@ -105,44 +90,34 @@ unsigned int gic_get_int(void)
 
 static unsigned int gic_irq_startup(unsigned int irq)
 {
-	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
 	irq -= _irqbase;
-	GIC_SET_INTR_MASK(irq, 1);
+	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
+	GIC_SET_INTR_MASK(irq);
 	return 0;
 }
 
 static void gic_irq_ack(unsigned int irq)
 {
-#if gic_wedgeb2bok == 0
-	unsigned long flags;
-#endif
-	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
 	irq -= _irqbase;
-	GIC_CLR_INTR_MASK(irq, 1);
+	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
+	GIC_CLR_INTR_MASK(irq);
 
-	if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) {
-		if (!gic_wedgeb2bok)
-			spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
+	if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE)
 		GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
-		if (!gic_wedgeb2bok) {
-			(void) GIC_REG(SHARED, GIC_SH_CONFIG);
-			spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
-		}
-	}
 }
 
 static void gic_mask_irq(unsigned int irq)
 {
-	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
 	irq -= _irqbase;
-	GIC_CLR_INTR_MASK(irq, 1);
+	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
+	GIC_CLR_INTR_MASK(irq);
 }
 
 static void gic_unmask_irq(unsigned int irq)
 {
-	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
 	irq -= _irqbase;
-	GIC_SET_INTR_MASK(irq, 1);
+	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
+	GIC_SET_INTR_MASK(irq);
 }
 
 #ifdef CONFIG_SMP
@@ -155,9 +130,8 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
 	unsigned long	flags;
 	int		i;
 
-	pr_debug(KERN_DEBUG "%s called\n", __func__);
 	irq -= _irqbase;
-
+	pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq);
 	cpumask_and(&tmp, cpumask, cpu_online_mask);
 	if (cpus_empty(tmp))
 		return -1;
@@ -168,13 +142,6 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
 		/* Re-route this IRQ */
 		GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
 
-		/*
-		 * FIXME: assumption that _intrmap is ordered and has no holes
-		 */
-
-		/* Update the intr_map */
-		_intrmap[irq].cpunum = first_cpu(tmp);
-
 		/* Update the pcpu_masks */
 		for (i = 0; i < NR_CPUS; i++)
 			clear_bit(irq, pcpu_masks[i].pcpu_mask);
@@ -201,8 +168,9 @@ static struct irq_chip gic_irq_controller = {
 #endif
 };
 
-static void __init setup_intr(unsigned int intr, unsigned int cpu,
-	unsigned int pin, unsigned int polarity, unsigned int trigtype)
+static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
+	unsigned int pin, unsigned int polarity, unsigned int trigtype,
+	unsigned int flags)
 {
 	/* Setup Intr to Pin mapping */
 	if (pin & GIC_MAP_TO_NMI_MSK) {
@@ -227,38 +195,43 @@ static void __init setup_intr(unsigned int intr, unsigned int cpu,
 	GIC_SET_TRIGGER(intr, trigtype);
 
 	/* Init Intr Masks */
-	GIC_SET_INTR_MASK(intr, 0);
+	GIC_CLR_INTR_MASK(intr);
+	/* Initialise per-cpu Interrupt software masks */
+	if (flags & GIC_FLAG_IPI)
+		set_bit(intr, pcpu_masks[cpu].pcpu_mask);
+	if (flags & GIC_FLAG_TRANSPARENT)
+		GIC_SET_INTR_MASK(intr);
+	if (trigtype == GIC_TRIG_EDGE)
+		gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE;
 }
 
-static void __init gic_basic_init(void)
+static void __init gic_basic_init(int numintrs, int numvpes,
+			struct gic_intr_map *intrmap, int mapsize)
 {
 	unsigned int i, cpu;
 
 	/* Setup defaults */
-	for (i = 0; i < GIC_NUM_INTRS; i++) {
+	for (i = 0; i < numintrs; i++) {
 		GIC_SET_POLARITY(i, GIC_POL_POS);
 		GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
-		GIC_SET_INTR_MASK(i, 0);
+		GIC_CLR_INTR_MASK(i);
+		if (i < GIC_NUM_INTRS)
+			gic_irq_flags[i] = 0;
 	}
 
 	/* Setup specifics */
-	for (i = 0; i < _mapsize; i++) {
-		cpu = _intrmap[i].cpunum;
+	for (i = 0; i < mapsize; i++) {
+		cpu = intrmap[i].cpunum;
 		if (cpu == X)
 			continue;
-
-		if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 &&
-					_intrmap[i].ipiflag == 0)
+		if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
 			continue;
-
-		setup_intr(_intrmap[i].intrnum,
-				_intrmap[i].cpunum,
-				_intrmap[i].pin,
-				_intrmap[i].polarity,
-				_intrmap[i].trigtype);
-		/* Initialise per-cpu Interrupt software masks */
-		if (_intrmap[i].ipiflag)
-			set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask);
+		gic_setup_intr(i,
+			intrmap[i].cpunum,
+			intrmap[i].pin,
+			intrmap[i].polarity,
+			intrmap[i].trigtype,
+			intrmap[i].flags);
 	}
 
 	vpe_local_setup(numvpes);
@@ -273,12 +246,11 @@ void __init gic_init(unsigned long gic_base_addr,
 		     unsigned int irqbase)
 {
 	unsigned int gicconfig;
+	int numvpes, numintrs;
 
 	_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
 						    gic_addrspace_size);
 	_irqbase = irqbase;
-	_intrmap = intr_map;
-	_mapsize = intr_map_size;
 
 	GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 	numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
@@ -288,7 +260,7 @@ void __init gic_init(unsigned long gic_base_addr,
 	numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 		  GIC_SH_CONFIG_NUMVPES_SHF;
 
-	pr_debug("%s called\n", __func__);
+	pr_debug("%s called\n", __FUNCTION__);
 
-	gic_basic_init();
+	gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
 }
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index e9ba8b3..92e3b56 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -385,24 +385,26 @@ static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
  * Interrupts and CPUs/Core Interrupts. The nature of the External
  * Interrupts is also defined here - polarity/trigger.
  */
+
+#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
-	{ GIC_EXT_INTR(0), 	X,	X,		X, 		X,		0 },
-	{ GIC_EXT_INTR(1), 	X,	X,		X, 		X,		0 },
-	{ GIC_EXT_INTR(2), 	X,	X,		X, 		X,		0 },
-	{ GIC_EXT_INTR(3), 	0,	GIC_CPU_INT0,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(4), 	0,	GIC_CPU_INT1,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(5), 	0,	GIC_CPU_INT2,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(6), 	0,	GIC_CPU_INT3,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(7), 	0,	GIC_CPU_INT4,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(8), 	0,	GIC_CPU_INT3,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(9), 	0,	GIC_CPU_INT3,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(10), 	X,	X,		X, 		X,		0 },
-	{ GIC_EXT_INTR(11), 	X,	X,		X, 		X,		0 },
-	{ GIC_EXT_INTR(12), 	0,	GIC_CPU_INT3,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(13), 	0,	GIC_MAP_TO_NMI_MSK,	GIC_POL_POS, GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(14), 	0,	GIC_MAP_TO_NMI_MSK,	GIC_POL_POS, GIC_TRIG_LEVEL,	0 },
-	{ GIC_EXT_INTR(15), 	X,	X,		X, 		X,		0 },
-/* This is the end of the general interrupts now we do IPI ones */
+	{ X, X,		   X,		X,		0 },
+	{ X, X,		   X,	 	X,		0 },
+	{ X, X,		   X,		X,		0 },
+	{ 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ X, X,		   X,		X,		0 },
+	{ X, X,		   X,		X,		0 },
+	{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+	{ X, X,		   X,		X,	        0 },
+	/* The remainder of this table is initialised by fill_ipi_map */
 };
 #endif
 
@@ -419,20 +421,35 @@ int __init gcmp_probe(unsigned long addr, unsigned long size)
 	gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
 
 	if (gcmp_present)
-		printk(KERN_DEBUG "GCMP present\n");
+		pr_debug("GCMP present\n");
 	return gcmp_present;
 }
 
+/* Return the number of IOCU's present */
+int __init gcmp_niocu(void)
+{
+  return gcmp_present ?
+    (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
+    0;
+}
+
+/* Set GCMP region attributes */
+void __init gcmp_setregion(int region, unsigned long base,
+			   unsigned long mask, int type)
+{
+	GCMPGCBn(CMxBASE, region) = base;
+	GCMPGCBn(CMxMASK, region) = mask | type;
+}
+
 #if defined(CONFIG_MIPS_MT_SMP)
 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
 {
 	int intr = baseintr + cpu;
-	gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr);
 	gic_intr_map[intr].cpunum = cpu;
 	gic_intr_map[intr].pin = cpupin;
 	gic_intr_map[intr].polarity = GIC_POL_POS;
 	gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
-	gic_intr_map[intr].ipiflag = 1;
+	gic_intr_map[intr].flags = GIC_FLAG_IPI;
 	ipi_map[cpu] |= (1 << (cpupin + 2));
 }
 
@@ -447,6 +464,12 @@ static void __init fill_ipi_map(void)
 }
 #endif
 
+void __init arch_init_ipiirq(int irq, struct irqaction *action)
+{
+	setup_irq(irq, action);
+	set_irq_handler(irq, handle_percpu_irq);
+}
+
 void __init arch_init_irq(void)
 {
 	init_i8259_irqs();
@@ -463,7 +486,7 @@ void __init arch_init_irq(void)
 		MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF;
 	}
 	if (gic_present)
-		printk(KERN_DEBUG "GIC present\n");
+		pr_debug("GIC present\n");
 
 	switch (mips_revision_sconid) {
 	case MIPS_REVISION_SCON_SOCIT:
@@ -526,16 +549,16 @@ void __init arch_init_irq(void)
 						&corehi_irqaction);
 	}
 
-#if defined(CONFIG_MIPS_MT_SMP)
 	if (gic_present) {
 		/* FIXME */
 		int i;
-
+#if defined(CONFIG_MIPS_MT_SMP)
 		gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
 		gic_resched_int_base = gic_call_int_base - NR_CPUS;
-
 		fill_ipi_map();
-		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
+#endif
+		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
+				ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
 		if (!gcmp_present) {
 			/* Enable the GIC */
 			i = REG(_msc01_biu_base, MSC01_SC_CFG);
@@ -543,7 +566,7 @@ void __init arch_init_irq(void)
 				(i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
 			pr_debug("GIC Enabled\n");
 		}
-
+#if defined(CONFIG_MIPS_MT_SMP)
 		/* set up ipi interrupts */
 		if (cpu_has_vint) {
 			set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
@@ -556,16 +579,14 @@ void __init arch_init_irq(void)
 		write_c0_status(0x1100dc00);
 		printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
 		for (i = 0; i < NR_CPUS; i++) {
-			setup_irq(MIPS_GIC_IRQ_BASE +
-					GIC_RESCHED_INT(i), &irq_resched);
-			setup_irq(MIPS_GIC_IRQ_BASE +
-					GIC_CALL_INT(i), &irq_call);
-			set_irq_handler(MIPS_GIC_IRQ_BASE +
-					GIC_RESCHED_INT(i), handle_percpu_irq);
-			set_irq_handler(MIPS_GIC_IRQ_BASE +
-					GIC_CALL_INT(i), handle_percpu_irq);
+			arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
+					 GIC_RESCHED_INT(i), &irq_resched);
+			arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
+					 GIC_CALL_INT(i), &irq_call);
 		}
+#endif
 	} else {
+#if defined(CONFIG_MIPS_MT_SMP)
 		/* set up ipi interrupts */
 		if (cpu_has_veic) {
 			set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
@@ -580,12 +601,8 @@ void __init arch_init_irq(void)
 			cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
 			cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
 		}
-
-		setup_irq(cpu_ipi_resched_irq, &irq_resched);
-		setup_irq(cpu_ipi_call_irq, &irq_call);
-
-		set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
-		set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
+		arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
+		arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
 	}
 #endif
 }
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index b974319..25994e6 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -27,7 +27,7 @@
 #include <linux/init.h>
 
 #include <asm/gt64120.h>
-
+#include <asm/gcmpregs.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/bonito64.h>
 #include <asm/mips-boards/msc01_pci.h>
@@ -201,7 +201,11 @@ void __init mips_pcibios_init(void)
 		msc_mem_resource.start = start & mask;
 		msc_mem_resource.end = (start & mask) | ~mask;
 		msc_controller.mem_offset = (start & mask) - (map & mask);
-
+#ifdef CONFIG_MIPS_CMP
+		if (gcmp_niocu())
+			gcmp_setregion(0, start, mask,
+				GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
+#endif
 		MSC_READ(MSC01_PCI_SC2PIOBASL, start);
 		MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
 		MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
@@ -209,7 +213,11 @@ void __init mips_pcibios_init(void)
 		msc_io_resource.end = (map & mask) | ~mask;
 		msc_controller.io_offset = 0;
 		ioport_resource.end = ~mask;
-
+#ifdef CONFIG_MIPS_CMP
+		if (gcmp_niocu())
+			gcmp_setregion(1, start, mask,
+				GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
+#endif
 		/* If ranges overlap I/O takes precedence.  */
 		start = start & mask;
 		end = start | ~mask;

[PATCH 11/15] Add missing memory barriers for correct operation of amon_cpu_start

[Raghu Gandham]

From: Chris Dearman <chris@mips.com>

Signed-off-by: Chris Dearman (chris@mips.com)
---

 arch/mips/mti-malta/malta-amon.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index df9e526..469d9b0 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -70,11 +70,12 @@ void amon_cpu_start(int cpu,
 	launch->sp = sp;
 	launch->a0 = a0;
 
-	/* Make sure target sees parameters before the go bit */
-	smp_mb();
-
+	smp_wmb();              /* Target must see parameters before go */
 	launch->flags |= LAUNCH_FGO;
+	smp_wmb();              /* Target must see go before we poll  */
+
 	while ((launch->flags & LAUNCH_FGONE) == 0)
 		;
+	smp_rmb();      /* Target will be updating flags soon */
 	pr_debug("launch: cpu%d gone!\n", cpu);
 }

[PATCH 12/15] Added coherentio command line option for DMA_NONCOHERENT kernel

[Raghu Gandham]

From: Chris Dearman <chris@mips.com>

Signed-off-by: Chris Dearman (chris@mips.com)
---

 arch/mips/mti-malta/malta-setup.c |  100 +++++++++++++++++++++++++++++++++++++
 1 files changed, 100 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index 69f5f9c..3f52c31 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -32,6 +32,7 @@
 #include <asm/mips-boards/maltaint.h>
 #include <asm/dma.h>
 #include <asm/traps.h>
+#include <asm/gcmpregs.h>
 #ifdef CONFIG_VT
 #include <linux/console.h>
 #endif
@@ -105,6 +106,103 @@ static void __init fd_activate(void)
 }
 #endif
 
+int coherentio = -1;
+static int __init setcoherentio(char *str)
+{
+	if (coherentio < 0)
+		pr_info("Command line checking done before"
+				" plat_setup_iocoherency!!\n");
+	if (coherentio == 0)
+		pr_info("Command line enabling coherentio"
+				" (this will break...)!!\n");
+
+	coherentio = 1;
+	pr_info("Hardware DMA cache coherency (command line)\n");
+	return 1;
+}
+__setup("coherentio", setcoherentio);
+
+static int __init setnocoherentio(char *str)
+{
+	if (coherentio < 0)
+		pr_info("Command line checking done before"
+				" plat_setup_iocoherency!!\n");
+	if (coherentio == 1)
+		pr_info("Command line disabling coherentio\n");
+
+	coherentio = 0;
+	pr_info("Software DMA cache coherency (command line)\n");
+	return 1;
+}
+__setup("nocoherentio", setnocoherentio);
+
+static int __init
+plat_enable_iocoherency(void)
+{
+	int supported = 0;
+	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
+		if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
+			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
+			pr_info("Enabled Bonito CPU coherency\n");
+			supported = 1;
+		}
+		if (strstr(prom_getcmdline(), "iobcuncached")) {
+			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
+			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
+				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
+				  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
+			pr_info("Disabled Bonito IOBC coherency\n");
+		} else {
+			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
+			BONITO_PCIMEMBASECFG |=
+				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
+				 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
+			pr_info("Enabled Bonito IOBC coherency\n");
+		}
+	} else if (gcmp_niocu() != 0) {
+		/* Nothing special needs to be done to enable coherency */
+		pr_info("CMP IOCU detected\n");
+		if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
+			pr_crit("IOCU OPERATION DISABLED BY SWITCH"
+				" - DEFAULTING TO SW IO COHERENCY\n");
+			return 0;
+		}
+		supported = 1;
+	}
+	return supported;
+}
+
+static void __init
+plat_setup_iocoherency(void)
+{
+#ifdef CONFIG_DMA_NONCOHERENT
+	/*
+	 * Kernel has been configured with software coherency
+	 * but we might choose to turn it off
+	 */
+	if (plat_enable_iocoherency()) {
+		if (coherentio == 0)
+			pr_info("Hardware DMA cache coherency supported"
+					" but disabled from command line\n");
+		else {
+			coherentio = 1;
+			printk(KERN_INFO "Hardware DMA cache coherency\n");
+		}
+	} else {
+		if (coherentio == 1)
+			pr_info("Hardware DMA cache coherency not supported"
+				" but enabled from command line\n");
+		else {
+			coherentio = 0;
+			pr_info("Software DMA cache coherency\n");
+		}
+	}
+#else
+	if (!plat_enable_iocoherency())
+		panic("Hardware DMA cache coherency not supported");
+#endif
+}
+
 #ifdef CONFIG_BLK_DEV_IDE
 static void __init pci_clock_check(void)
 {
@@ -207,6 +305,8 @@ void __init plat_mem_setup(void)
 	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
 		bonito_quirks_setup();
 
+	plat_setup_iocoherency();
+
 #ifdef CONFIG_BLK_DEV_IDE
 	pci_clock_check();
 #endif

[PATCH 13/15] Avoid accessing GCMP registers when they are not present

[Raghu Gandham]

From: Jaidev Patwardhan <jaidev@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/mti-malta/malta-int.c |   16 +++++++++++++---
 1 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 92e3b56..63e7161 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -413,6 +413,11 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
  */
 int __init gcmp_probe(unsigned long addr, unsigned long size)
 {
+	if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
+		gcmp_present = 0;
+		return gcmp_present;
+	}
+
 	if (gcmp_present >= 0)
 		return gcmp_present;
 
@@ -481,9 +486,14 @@ void __init arch_init_irq(void)
 		GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
 		gic_present = 1;
 	} else {
-		_msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
-		gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
-		MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF;
+		if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
+			_msc01_biu_base = (unsigned long)
+					ioremap_nocache(MSC01_BIU_REG_BASE,
+						MSC01_BIU_ADDRSPACE_SZ);
+			gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
+					MSC01_SC_CFG_GICPRES_MSK) >>
+					MSC01_SC_CFG_GICPRES_SHF;
+		}
 	}
 	if (gic_present)
 		pr_debug("GIC present\n");

[PATCH 14/15] Avoid queing multiple reschedule IPI's in SMTC

[Raghu Gandham]

From: Jaidev Patwardhan <jaidev@mips.com>

Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/include/asm/smtc_ipi.h |    5 +++--
 arch/mips/kernel/smtc.c          |   33 +++++++++++++++++++++++++++++----
 2 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h
index 8ce5175..832b8be 100644
--- a/arch/mips/include/asm/smtc_ipi.h
+++ b/arch/mips/include/asm/smtc_ipi.h
@@ -23,8 +23,8 @@ struct smtc_ipi {
 	void *arg;
 	int dest;
 #ifdef	SMTC_IPI_DEBUG
-	int sender;
-	long stamp;
+	unsigned sender;
+	unsigned long long stamp;
 #endif /* SMTC_IPI_DEBUG */
 };
 
@@ -45,6 +45,7 @@ struct smtc_ipi_q {
 	spinlock_t lock;
 	struct smtc_ipi *tail;
 	int depth;
+	int resched_flag;	/* reschedule already queued */
 };
 
 static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 8a0626c..69240c4 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -75,7 +75,6 @@ unsigned long irq_hwmask[NR_IRQS];
 
 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
 
-
 /*
  * Number of InterProcessor Interrupt (IPI) message buffers to allocate
  */
@@ -388,6 +387,7 @@ void smtc_prepare_cpus(int cpus)
 		IPIQ[i].head = IPIQ[i].tail = NULL;
 		spin_lock_init(&IPIQ[i].lock);
 		IPIQ[i].depth = 0;
+		IPIQ[i].resched_flag = 0; /* No reschedules queued initially */
 	}
 
 	/* cpu_data index starts at zero */
@@ -738,11 +738,24 @@ void smtc_forward_irq(unsigned int irq)
 static void smtc_ipi_qdump(void)
 {
 	int i;
+	struct smtc_ipi *temp;
 
 	for (i = 0; i < NR_CPUS ;i++) {
-		printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
+		pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
 			i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
 			IPIQ[i].depth);
+		temp = IPIQ[i].head;
+
+		while (temp != IPIQ[i].tail) {
+			pr_debug("%d %d %d: ", temp->type, temp->dest,
+			       (int)temp->arg);
+#ifdef	SMTC_IPI_DEBUG
+		    pr_debug("%u %lu\n", temp->sender, temp->stamp);
+#else
+		    pr_debug("\n");
+#endif
+		    temp = temp->flink;
+		}
 	}
 }
 
@@ -781,11 +794,15 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
 	int mtflags;
 	unsigned long tcrestart;
 	extern void r4k_wait_irqoff(void), __pastwait(void);
+	int set_resched_flag = (type == LINUX_SMP_IPI &&
+				action == SMP_RESCHEDULE_YOURSELF);
 
 	if (cpu == smp_processor_id()) {
 		printk("Cannot Send IPI to self!\n");
 		return;
 	}
+	if (set_resched_flag && IPIQ[cpu].resched_flag != 0)
+		return; /* There is a reschedule queued already */
 	/* Set up a descriptor, to be delivered either promptly or queued */
 	pipi = smtc_ipi_dq(&freeIPIq);
 	if (pipi == NULL) {
@@ -798,6 +815,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
 	pipi->dest = cpu;
 	if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
 		/* If not on same VPE, enqueue and send cross-VPE interrupt */
+		IPIQ[cpu].resched_flag |= set_resched_flag;
 		smtc_ipi_nq(&IPIQ[cpu], pipi);
 		LOCK_CORE_PRA();
 		settc(cpu_data[cpu].tc_id);
@@ -844,6 +862,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
 			 */
 			write_tc_c0_tchalt(0);
 			UNLOCK_CORE_PRA();
+			IPIQ[cpu].resched_flag |= set_resched_flag;
 			smtc_ipi_nq(&IPIQ[cpu], pipi);
 		} else {
 postdirect:
@@ -993,12 +1012,15 @@ void deferred_smtc_ipi(void)
 		 * already enabled.
 		 */
 		local_irq_save(flags);
-
 		spin_lock(&q->lock);
 		pipi = __smtc_ipi_dq(q);
 		spin_unlock(&q->lock);
-		if (pipi != NULL)
+		if (pipi != NULL) {
+			if (pipi->type == LINUX_SMP_IPI &&
+			    (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
+				IPIQ[q].resched_flag = 0;
 			ipi_decode(pipi);
+		}
 		/*
 		 * The use of the __raw_local restore isn't
 		 * as obviously necessary here as in smtc_ipi_replay(),
@@ -1079,6 +1101,9 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
 				 * with interrupts off
 				 */
 				local_irq_save(flags);
+				if (pipi->type == LINUX_SMP_IPI &&
+				    (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
+					IPIQ[cpu].resched_flag = 0;
 				ipi_decode(pipi);
 				local_irq_restore(flags);
 			}

[PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes

[Raghu Gandham]

From: Kurt Martin <kurt@mips.com>

Signed-off-by: Jaidev Patwardhan <jaidev@mips.com>
	Signed-off-by: Chris Dearman <chris@mips.com>
---

 arch/mips/kernel/smtc.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 69240c4..3498b82 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -481,6 +481,18 @@ void smtc_prepare_cpus(int cpus)
 			 */
 			if (tc != 0) {
 				smtc_tc_setup(vpe, tc, cpu);
+				if (vpe != 0) {
+					/*
+					 * Set MVP bit (possibly again).  Do it
+					 * here to catch CPUs that have no TCs
+					 * bound to the VPE at reset.  In that
+					 * case, a TC must be bound to the VPE
+					 * before we can set VPEControl[MVP]
+					 */
+					write_vpe_c0_vpeconf0(
+						read_vpe_c0_vpeconf0() |
+						VPECONF0_MVP);
+				}
 				cpu++;
 			}
 			printk(" %d", tc);

Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes

[Kevin D. Kissell]

Note that, regardless of the reset state, smtc_configure_tlb() should 
have at least temporarily bound TC 1 to VPE1, which may be why this 
never seemed to be a problem on the 34K.  If one wants to support 
designs with more than 2 VPEs, then this is probably one of the things 
that needs to be fixed.  That having been said, rather than adding a 
usually-redundant write_vpe_c0_vpeconf0() in that clause, wouldn't it be 
cleaner to just move the MVP setting from the top of the loop to the 
point in the loop just after the TCs have been bound to the VPE in 
question, i.e.,

 454                 if (slop) {
 455                         if (tc != 0) {
 456                                 smtc_tc_setup(vpe,tc, cpu);
 457                                 cpu++;
 458                         }
 459                         printk(" %d", tc);
 460                         tc++;
 461                         slop--;
 462                 }

                        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | 
VPECONF0_MVP);

 463                 if (vpe != 0) {
 464                         /*
 465                          * Clear any stale software interrupts from 
VPE's Cause
 466                          */

This should definitely be OK for a 34K, because it's being executed by 
TC0 in VPE0 and the reset state of VPE0 has MVP set.  If it weren't, 
smtc_configure_tlb() would have failed.

          Regards,

          Kevin K.

Raghu Gandham wrote:
> From: Kurt Martin <kurt@mips.com>
>
> Signed-off-by: Jaidev Patwardhan <jaidev@mips.com>
> 	Signed-off-by: Chris Dearman <chris@mips.com>
> ---
>
>  arch/mips/kernel/smtc.c |   12 ++++++++++++
>  1 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
> index 69240c4..3498b82 100644
> --- a/arch/mips/kernel/smtc.c
> +++ b/arch/mips/kernel/smtc.c
> @@ -481,6 +481,18 @@ void smtc_prepare_cpus(int cpus)
>  			 */
>  			if (tc != 0) {
>  				smtc_tc_setup(vpe, tc, cpu);
> +				if (vpe != 0) {
> +					/*
> +					 * Set MVP bit (possibly again).  Do it
> +					 * here to catch CPUs that have no TCs
> +					 * bound to the VPE at reset.  In that
> +					 * case, a TC must be bound to the VPE
> +					 * before we can set VPEControl[MVP]
> +					 */
> +					write_vpe_c0_vpeconf0(
> +						read_vpe_c0_vpeconf0() |
> +						VPECONF0_MVP);
> +				}
>  				cpu++;
>  			}
>  			printk(" %d", tc);
>
>
>   

RE: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes

[Gandham, Raghu]

> -----Original Message-----
> From: Kevin D. Kissell [mailto:kevink@paralogos.com]
> Sent: Wednesday, July 01, 2009 9:02 PM
> To: Gandham, Raghu
> Cc: linux-mips@linux-mips.org; Dearman, Chris
> Subject: Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE
> bindings when doing cross VPE writes
> 
> Note that, regardless of the reset state, smtc_configure_tlb() should
> have at least temporarily bound TC 1 to VPE1, which may be why this
> never seemed to be a problem on the 34K.  If one wants to support
> designs with more than 2 VPEs, then this is probably one of the things
> that needs to be fixed.  That having been said, rather than adding a
> usually-redundant write_vpe_c0_vpeconf0() in that clause, wouldn't it
be
> cleaner to just move the MVP setting from the top of the loop to the
> point in the loop just after the TCs have been bound to the VPE in
> question, i.e.,
> 
>  454                 if (slop) {
>  455                         if (tc != 0) {
>  456                                 smtc_tc_setup(vpe,tc, cpu);
>  457                                 cpu++;
>  458                         }
>  459                         printk(" %d", tc);
>  460                         tc++;
>  461                         slop--;
>  462                 }
> 
>                         write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() |
> VPECONF0_MVP);
> 
>  463                 if (vpe != 0) {
>  464                         /*
>  465                          * Clear any stale software interrupts
from
> VPE's Cause
>  466                          */
> 
> This should definitely be OK for a 34K, because it's being executed by
> TC0 in VPE0 and the reset state of VPE0 has MVP set.  If it weren't,
> smtc_configure_tlb() would have failed.
> 
>           Regards,
> 
>           Kevin K.


I will resend this patch with your suggestion.

Thanks,
Raghu

> 
> Raghu Gandham wrote:
> > From: Kurt Martin <kurt@mips.com>
> >
> > Signed-off-by: Jaidev Patwardhan <jaidev@mips.com>
> > 	Signed-off-by: Chris Dearman <chris@mips.com>
> > ---
> >
> >  arch/mips/kernel/smtc.c |   12 ++++++++++++
> >  1 files changed, 12 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
> > index 69240c4..3498b82 100644
> > --- a/arch/mips/kernel/smtc.c
> > +++ b/arch/mips/kernel/smtc.c
> > @@ -481,6 +481,18 @@ void smtc_prepare_cpus(int cpus)
> >  			 */
> >  			if (tc != 0) {
> >  				smtc_tc_setup(vpe, tc, cpu);
> > +				if (vpe != 0) {
> > +					/*
> > +					 * Set MVP bit (possibly again).
Do it
> > +					 * here to catch CPUs that have
no TCs
> > +					 * bound to the VPE at reset.
In that
> > +					 * case, a TC must be bound to
the VPE
> > +					 * before we can set
VPEControl[MVP]
> > +					 */
> > +					write_vpe_c0_vpeconf0(
> > +						read_vpe_c0_vpeconf0() |
> > +						VPECONF0_MVP);
> > +				}
> >  				cpu++;
> >  			}
> >  			printk(" %d", tc);
> >
> >
> >

RE: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes

[Gandham, Raghu]

> -----Original Message-----
> From: Kevin D. Kissell [mailto:kevink@paralogos.com]
> Sent: Wednesday, July 01, 2009 9:02 PM
> To: Gandham, Raghu
> Cc: linux-mips@linux-mips.org; Dearman, Chris
> Subject: Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE
> bindings when doing cross VPE writes
> 
> Note that, regardless of the reset state, smtc_configure_tlb() should
> have at least temporarily bound TC 1 to VPE1, which may be why this
> never seemed to be a problem on the 34K.  If one wants to support
> designs with more than 2 VPEs, then this is probably one of the things
> that needs to be fixed.  That having been said, rather than adding a
> usually-redundant write_vpe_c0_vpeconf0() in that clause, wouldn't it
be
> cleaner to just move the MVP setting from the top of the loop to the
> point in the loop just after the TCs have been bound to the VPE in
> question, i.e.,
> 
>  454                 if (slop) {
>  455                         if (tc != 0) {
>  456                                 smtc_tc_setup(vpe,tc, cpu);
>  457                                 cpu++;
>  458                         }
>  459                         printk(" %d", tc);
>  460                         tc++;
>  461                         slop--;
>  462                 }
> 
>                         write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() |
> VPECONF0_MVP);
> 
>  463                 if (vpe != 0) {
>  464                         /*
>  465                          * Clear any stale software interrupts
from
> VPE's Cause
>  466                          */
> 
> This should definitely be OK for a 34K, because it's being executed by
> TC0 in VPE0 and the reset state of VPE0 has MVP set.  If it weren't,
> smtc_configure_tlb() would have failed.
> 
>           Regards,
> 
>           Kevin K.


I will resend this patch with your suggestion.

Thanks,
Raghu

> 
> Raghu Gandham wrote:
> > From: Kurt Martin <kurt@mips.com>
> >
> > Signed-off-by: Jaidev Patwardhan <jaidev@mips.com>
> > 	Signed-off-by: Chris Dearman <chris@mips.com>
> > ---
> >
> >  arch/mips/kernel/smtc.c |   12 ++++++++++++
> >  1 files changed, 12 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
> > index 69240c4..3498b82 100644
> > --- a/arch/mips/kernel/smtc.c
> > +++ b/arch/mips/kernel/smtc.c
> > @@ -481,6 +481,18 @@ void smtc_prepare_cpus(int cpus)
> >  			 */
> >  			if (tc != 0) {
> >  				smtc_tc_setup(vpe, tc, cpu);
> > +				if (vpe != 0) {
> > +					/*
> > +					 * Set MVP bit (possibly again).
Do it
> > +					 * here to catch CPUs that have
no TCs
> > +					 * bound to the VPE at reset.
In that
> > +					 * case, a TC must be bound to
the VPE
> > +					 * before we can set
VPEControl[MVP]
> > +					 */
> > +					write_vpe_c0_vpeconf0(
> > +						read_vpe_c0_vpeconf0() |
> > +						VPECONF0_MVP);
> > +				}
> >  				cpu++;
> >  			}
> >  			printk(" %d", tc);
> >
> >
> >

Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes

[Kevin D. Kissell]

[-- Attachment #1: Type: text/plain, Size: 2120 bytes --]

Gandham, Raghu wrote:
>   
>> -----Original Message-----
>> From: Kevin D. Kissell [mailto:kevink@paralogos.com]
>> Sent: Wednesday, July 01, 2009 9:02 PM
>> To: Gandham, Raghu
>> Cc: linux-mips@linux-mips.org; Dearman, Chris
>> Subject: Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE
>> bindings when doing cross VPE writes
>>
>> Note that, regardless of the reset state, smtc_configure_tlb() should
>> have at least temporarily bound TC 1 to VPE1, which may be why this
>> never seemed to be a problem on the 34K.  If one wants to support
>> designs with more than 2 VPEs, then this is probably one of the things
>> that needs to be fixed.  That having been said, rather than adding a
>> usually-redundant write_vpe_c0_vpeconf0() in that clause, wouldn't it
>>     
> be
>   
>> cleaner to just move the MVP setting from the top of the loop to the
>> point in the loop just after the TCs have been bound to the VPE in
>> question, i.e.,
>>
>>  454                 if (slop) {
>>  455                         if (tc != 0) {
>>  456                                 smtc_tc_setup(vpe,tc, cpu);
>>  457                                 cpu++;
>>  458                         }
>>  459                         printk(" %d", tc);
>>  460                         tc++;
>>  461                         slop--;
>>  462                 }
>>
>>                         write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() |
>> VPECONF0_MVP);
>>
>>  463                 if (vpe != 0) {
>>  464                         /*
>>  465                          * Clear any stale software interrupts
>>     
> from
>   
>> VPE's Cause
>>  466                          */
>>
>> This should definitely be OK for a 34K, because it's being executed by
>> TC0 in VPE0 and the reset state of VPE0 has MVP set.  If it weren't,
>> smtc_configure_tlb() would have failed.
>>
>>           Regards,
>>
>>           Kevin K.
>>     
>
>
> I will resend this patch with your suggestion.
>
> Thanks,
> Raghu
>   
Just make sure it works, first!  ;o)  I'm thousands of miles away from 
my build/test systems.

          Regards,

          Kevn K.

[-- Attachment #2: Type: text/html, Size: 2850 bytes --]

RE: [PATCH 00/15] Port changes from linux-mti

[Gandham, Raghu]

> The following series of patches port the changes in 
> linux-mti.git repository to the head of tree. 
> ---
> 
> Chris Dearman (9):
>       Added coherentio command line option for DMA_NONCOHERENT kernel
>       Add missing memory barriers for correct operation of 
> amon_cpu_start
>       Port of GIC related changes from MTI branch.
>       Add debug prints during CPU intialization.
>       APRP Patch04: Propagate final value of max_low_pfn to max_pfn
>       [MTI] Enable PIIX4 PCI2.1 compliancy on Malta
>       [MTI] MIPS secondary cache supports 64 byte line size.
>       Fix accesses to device registers on MIPS boards
>       [MTI] Clean up SPRAM support a little
> 
> Jaidev Patwardhan (2):
>       Avoid queing multiple reschedule IPI's in SMTC
>       Avoid accessing GCMP registers when they are not present
> 
> Kurt Martin (1):
>       Do not rely on the initial state of TC/VPE bindings 
> when doing cross VPE writes
> 
> Raghu Gandham (1):
>       Fix compiler warning in vpe.c
> 
> Robin Randhawa (2):
>       Fix absd emulation
>       Due to some broken bitfiles, we can't trust IntCtl
> 
> 
>  arch/mips/Kconfig                 |    1 
>  arch/mips/include/asm/gcmpregs.h  |   18 ++--
>  arch/mips/include/asm/gic.h       |  188 
> ++++---------------------------------
>  arch/mips/include/asm/irq.h       |    1 
>  arch/mips/include/asm/smtc_ipi.h  |    5 +
>  arch/mips/include/asm/spram.h     |   10 ++
>  arch/mips/kernel/cpu-probe.c      |    8 --
>  arch/mips/kernel/irq-gic.c        |  116 +++++++++--------------
>  arch/mips/kernel/setup.c          |    3 -
>  arch/mips/kernel/smp-mt.c         |   10 ++
>  arch/mips/kernel/smtc.c           |   45 ++++++++-
>  arch/mips/kernel/spram.c          |    5 -
>  arch/mips/kernel/traps.c          |    4 +
>  arch/mips/kernel/vpe.c            |    3 -
>  arch/mips/math-emu/dp_simple.c    |   11 +-
>  arch/mips/math-emu/sp_simple.c    |    3 -
>  arch/mips/mti-malta/malta-amon.c  |    7 +
>  arch/mips/mti-malta/malta-int.c   |  115 ++++++++++++++---------
>  arch/mips/mti-malta/malta-pci.c   |   14 ++-
>  arch/mips/mti-malta/malta-setup.c |  111 
> ++++++++++++++++++++++  20 files changed, 351 insertions(+), 
> 327 deletions(-)  create mode 100644 arch/mips/include/asm/spram.h

I am resending the series as smaller patches after fixing a couple of
typos. 

Thanks,
Raghu

RE: [PATCH 00/15] Port changes from linux-mti

[Gandham, Raghu]

> The following series of patches port the changes in 
> linux-mti.git repository to the head of tree. 
> ---
> 
> Chris Dearman (9):
>       Added coherentio command line option for DMA_NONCOHERENT kernel
>       Add missing memory barriers for correct operation of 
> amon_cpu_start
>       Port of GIC related changes from MTI branch.
>       Add debug prints during CPU intialization.
>       APRP Patch04: Propagate final value of max_low_pfn to max_pfn
>       [MTI] Enable PIIX4 PCI2.1 compliancy on Malta
>       [MTI] MIPS secondary cache supports 64 byte line size.
>       Fix accesses to device registers on MIPS boards
>       [MTI] Clean up SPRAM support a little
> 
> Jaidev Patwardhan (2):
>       Avoid queing multiple reschedule IPI's in SMTC
>       Avoid accessing GCMP registers when they are not present
> 
> Kurt Martin (1):
>       Do not rely on the initial state of TC/VPE bindings 
> when doing cross VPE writes
> 
> Raghu Gandham (1):
>       Fix compiler warning in vpe.c
> 
> Robin Randhawa (2):
>       Fix absd emulation
>       Due to some broken bitfiles, we can't trust IntCtl
> 
> 
>  arch/mips/Kconfig                 |    1 
>  arch/mips/include/asm/gcmpregs.h  |   18 ++--
>  arch/mips/include/asm/gic.h       |  188 
> ++++---------------------------------
>  arch/mips/include/asm/irq.h       |    1 
>  arch/mips/include/asm/smtc_ipi.h  |    5 +
>  arch/mips/include/asm/spram.h     |   10 ++
>  arch/mips/kernel/cpu-probe.c      |    8 --
>  arch/mips/kernel/irq-gic.c        |  116 +++++++++--------------
>  arch/mips/kernel/setup.c          |    3 -
>  arch/mips/kernel/smp-mt.c         |   10 ++
>  arch/mips/kernel/smtc.c           |   45 ++++++++-
>  arch/mips/kernel/spram.c          |    5 -
>  arch/mips/kernel/traps.c          |    4 +
>  arch/mips/kernel/vpe.c            |    3 -
>  arch/mips/math-emu/dp_simple.c    |   11 +-
>  arch/mips/math-emu/sp_simple.c    |    3 -
>  arch/mips/mti-malta/malta-amon.c  |    7 +
>  arch/mips/mti-malta/malta-int.c   |  115 ++++++++++++++---------
>  arch/mips/mti-malta/malta-pci.c   |   14 ++-
>  arch/mips/mti-malta/malta-setup.c |  111 
> ++++++++++++++++++++++  20 files changed, 351 insertions(+), 
> 327 deletions(-)  create mode 100644 arch/mips/include/asm/spram.h

I am resending the series as smaller patches after fixing a couple of
typos. 

Thanks,
Raghu

Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes

[Ralf Baechle]

On Thu, Jul 02, 2009 at 02:46:33PM -0700, Gandham, Raghu wrote:

> > From: Kevin D. Kissell [mailto:kevink@paralogos.com]
> > Sent: Wednesday, July 01, 2009 9:02 PM
> > To: Gandham, Raghu
> > Cc: linux-mips@linux-mips.org; Dearman, Chris
> > Subject: Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE
> > bindings when doing cross VPE writes
> > 
> > Note that, regardless of the reset state, smtc_configure_tlb() should
> > have at least temporarily bound TC 1 to VPE1, which may be why this
> > never seemed to be a problem on the 34K.  If one wants to support
> > designs with more than 2 VPEs, then this is probably one of the things
> > that needs to be fixed.  That having been said, rather than adding a
> > usually-redundant write_vpe_c0_vpeconf0() in that clause, wouldn't it
> be
> > cleaner to just move the MVP setting from the top of the loop to the
> > point in the loop just after the TCs have been bound to the VPE in
> > question, i.e.,
> > 
> >  454                 if (slop) {
> >  455                         if (tc != 0) {
> >  456                                 smtc_tc_setup(vpe,tc, cpu);
> >  457                                 cpu++;
> >  458                         }
> >  459                         printk(" %d", tc);
> >  460                         tc++;
> >  461                         slop--;
> >  462                 }
> > 
> >                         write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() |
> > VPECONF0_MVP);
> > 
> >  463                 if (vpe != 0) {
> >  464                         /*
> >  465                          * Clear any stale software interrupts
> from
> > VPE's Cause
> >  466                          */
> > 
> > This should definitely be OK for a 34K, because it's being executed by
> > TC0 in VPE0 and the reset state of VPE0 has MVP set.  If it weren't,
> > smtc_configure_tlb() would have failed.
> > 
> >           Regards,
> > 
> >           Kevin K.
> 
> 
> I will resend this patch with your suggestion.

Ping?  Don't think I ever received that, if you sent it.

  Ralf

RE: [PATCH 15/15] Do not rely on the initial state of TC/VPEbindings when doing cross VPE writes

[Gandham, Raghu]

 

> -----Original Message-----
> From: Ralf Baechle [mailto:ralf@linux-mips.org] 
> Sent: Monday, October 12, 2009 9:18 AM
> To: Gandham, Raghu
> Cc: Kevin D. Kissell; linux-mips@linux-mips.org; Dearman, Chris
> Subject: Re: [PATCH 15/15] Do not rely on the initial state 
> of TC/VPEbindings when doing cross VPE writes
> 
> On Thu, Jul 02, 2009 at 02:46:33PM -0700, Gandham, Raghu wrote:
> 
> > > From: Kevin D. Kissell [mailto:kevink@paralogos.com]
> > > Sent: Wednesday, July 01, 2009 9:02 PM
> > > To: Gandham, Raghu
> > > Cc: linux-mips@linux-mips.org; Dearman, Chris
> > > Subject: Re: [PATCH 15/15] Do not rely on the initial state of 
> > > TC/VPE bindings when doing cross VPE writes
> > > 
> > > Note that, regardless of the reset state, smtc_configure_tlb() 
> > > should have at least temporarily bound TC 1 to VPE1, which may be 
> > > why this never seemed to be a problem on the 34K.  If one 
> wants to 
> > > support designs with more than 2 VPEs, then this is 
> probably one of 
> > > the things that needs to be fixed.  That having been said, rather 
> > > than adding a usually-redundant write_vpe_c0_vpeconf0() in that 
> > > clause, wouldn't it
> > be
> > > cleaner to just move the MVP setting from the top of the 
> loop to the 
> > > point in the loop just after the TCs have been bound to 
> the VPE in 
> > > question, i.e.,
> > > 
> > >  454                 if (slop) {
> > >  455                         if (tc != 0) {
> > >  456                                 smtc_tc_setup(vpe,tc, cpu);
> > >  457                                 cpu++;
> > >  458                         }
> > >  459                         printk(" %d", tc);
> > >  460                         tc++;
> > >  461                         slop--;
> > >  462                 }
> > > 
> > >                         
> write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() 
> > > | VPECONF0_MVP);
> > > 
> > >  463                 if (vpe != 0) {
> > >  464                         /*
> > >  465                          * Clear any stale software 
> interrupts
> > from
> > > VPE's Cause
> > >  466                          */
> > > 
> > > This should definitely be OK for a 34K, because it's 
> being executed 
> > > by TC0 in VPE0 and the reset state of VPE0 has MVP set.  If it 
> > > weren't,
> > > smtc_configure_tlb() would have failed.
> > > 
> > >           Regards,
> > > 
> > >           Kevin K.
> > 
> > 
> > I will resend this patch with your suggestion.
> 
> Ping?  Don't think I ever received that, if you sent it.
I resent the patch and it got checked-in. It is not appended to this
mail thread though. 
http://www.linux-mips.org/git?p=linux.git;a=commitdiff;h=d8e5f9fe5dab0e0
7985f2456cb6cc57788f53131

Thanks,
Raghu

> 
>   Ralf
> 

RE: [PATCH 15/15] Do not rely on the initial state of TC/VPEbindings when doing cross VPE writes

[Gandham, Raghu]

 

> -----Original Message-----
> From: Ralf Baechle [mailto:ralf@linux-mips.org] 
> Sent: Monday, October 12, 2009 9:18 AM
> To: Gandham, Raghu
> Cc: Kevin D. Kissell; linux-mips@linux-mips.org; Dearman, Chris
> Subject: Re: [PATCH 15/15] Do not rely on the initial state 
> of TC/VPEbindings when doing cross VPE writes
> 
> On Thu, Jul 02, 2009 at 02:46:33PM -0700, Gandham, Raghu wrote:
> 
> > > From: Kevin D. Kissell [mailto:kevink@paralogos.com]
> > > Sent: Wednesday, July 01, 2009 9:02 PM
> > > To: Gandham, Raghu
> > > Cc: linux-mips@linux-mips.org; Dearman, Chris
> > > Subject: Re: [PATCH 15/15] Do not rely on the initial state of 
> > > TC/VPE bindings when doing cross VPE writes
> > > 
> > > Note that, regardless of the reset state, smtc_configure_tlb() 
> > > should have at least temporarily bound TC 1 to VPE1, which may be 
> > > why this never seemed to be a problem on the 34K.  If one 
> wants to 
> > > support designs with more than 2 VPEs, then this is 
> probably one of 
> > > the things that needs to be fixed.  That having been said, rather 
> > > than adding a usually-redundant write_vpe_c0_vpeconf0() in that 
> > > clause, wouldn't it
> > be
> > > cleaner to just move the MVP setting from the top of the 
> loop to the 
> > > point in the loop just after the TCs have been bound to 
> the VPE in 
> > > question, i.e.,
> > > 
> > >  454                 if (slop) {
> > >  455                         if (tc != 0) {
> > >  456                                 smtc_tc_setup(vpe,tc, cpu);
> > >  457                                 cpu++;
> > >  458                         }
> > >  459                         printk(" %d", tc);
> > >  460                         tc++;
> > >  461                         slop--;
> > >  462                 }
> > > 
> > >                         
> write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() 
> > > | VPECONF0_MVP);
> > > 
> > >  463                 if (vpe != 0) {
> > >  464                         /*
> > >  465                          * Clear any stale software 
> interrupts
> > from
> > > VPE's Cause
> > >  466                          */
> > > 
> > > This should definitely be OK for a 34K, because it's 
> being executed 
> > > by TC0 in VPE0 and the reset state of VPE0 has MVP set.  If it 
> > > weren't,
> > > smtc_configure_tlb() would have failed.
> > > 
> > >           Regards,
> > > 
> > >           Kevin K.
> > 
> > 
> > I will resend this patch with your suggestion.
> 
> Ping?  Don't think I ever received that, if you sent it.
I resent the patch and it got checked-in. It is not appended to this
mail thread though. 
http://www.linux-mips.org/git?p=linux.git;a=commitdiff;h=d8e5f9fe5dab0e0
7985f2456cb6cc57788f53131

Thanks,
Raghu

> 
>   Ralf
> 

Re: [PATCH 15/15] Do not rely on the initial state of TC/VPEbindings when doing cross VPE writes

[Ralf Baechle]

On Mon, Oct 12, 2009 at 01:20:49PM -0700, Gandham, Raghu wrote:

> > -----Original Message-----
> > From: Ralf Baechle [mailto:ralf@linux-mips.org] 
> > Sent: Monday, October 12, 2009 9:18 AM
> > To: Gandham, Raghu
> > Cc: Kevin D. Kissell; linux-mips@linux-mips.org; Dearman, Chris
> > Subject: Re: [PATCH 15/15] Do not rely on the initial state 
> > of TC/VPEbindings when doing cross VPE writes
> > 
> > On Thu, Jul 02, 2009 at 02:46:33PM -0700, Gandham, Raghu wrote:
> > 
> > > > From: Kevin D. Kissell [mailto:kevink@paralogos.com]
> > > > Sent: Wednesday, July 01, 2009 9:02 PM
> > > > To: Gandham, Raghu
> > > > Cc: linux-mips@linux-mips.org; Dearman, Chris
> > > > Subject: Re: [PATCH 15/15] Do not rely on the initial state of 
> > > > TC/VPE bindings when doing cross VPE writes
> > > > 
> > > > Note that, regardless of the reset state, smtc_configure_tlb() 
> > > > should have at least temporarily bound TC 1 to VPE1, which may be 
> > > > why this never seemed to be a problem on the 34K.  If one 
> > wants to 
> > > > support designs with more than 2 VPEs, then this is 
> > probably one of 
> > > > the things that needs to be fixed.  That having been said, rather 
> > > > than adding a usually-redundant write_vpe_c0_vpeconf0() in that 
> > > > clause, wouldn't it
> > > be
> > > > cleaner to just move the MVP setting from the top of the 
> > loop to the 
> > > > point in the loop just after the TCs have been bound to 
> > the VPE in 
> > > > question, i.e.,
> > > > 
> > > >  454                 if (slop) {
> > > >  455                         if (tc != 0) {
> > > >  456                                 smtc_tc_setup(vpe,tc, cpu);
> > > >  457                                 cpu++;
> > > >  458                         }
> > > >  459                         printk(" %d", tc);
> > > >  460                         tc++;
> > > >  461                         slop--;
> > > >  462                 }
> > > > 
> > > >                         
> > write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() 
> > > > | VPECONF0_MVP);
> > > > 
> > > >  463                 if (vpe != 0) {
> > > >  464                         /*
> > > >  465                          * Clear any stale software 
> > interrupts
> > > from
> > > > VPE's Cause
> > > >  466                          */
> > > > 
> > > > This should definitely be OK for a 34K, because it's 
> > being executed 
> > > > by TC0 in VPE0 and the reset state of VPE0 has MVP set.  If it 
> > > > weren't,
> > > > smtc_configure_tlb() would have failed.
> > > > 
> > > >           Regards,
> > > > 
> > > >           Kevin K.
> > > 
> > > 
> > > I will resend this patch with your suggestion.
> > 
> > Ping?  Don't think I ever received that, if you sent it.
> I resent the patch and it got checked-in. It is not appended to this
> mail thread though. 
> http://www.linux-mips.org/git?p=linux.git;a=commitdiff;h=d8e5f9fe5dab0e0
> 7985f2456cb6cc57788f53131

Ah, ok.  Thanks!

  Ralf