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From: Ralf Baechle <ralf@linux-mips.org>
To: figo zhang <figo1802@gmail.com>
Cc: linux-mips@linux-mips.org
Subject: Re: how i can know the linux-mips implememt cache strategy?
Date: Wed, 18 Nov 2009 12:44:32 +0100	[thread overview]
Message-ID: <20091118114432.GA17418@linux-mips.org> (raw)
In-Reply-To: <c6ed1ac50911171859k24685b32m237afd68f63c626f@mail.gmail.com>

On Wed, Nov 18, 2009 at 10:59:43AM +0800, figo zhang wrote:

> I am porting 24KEC soc to linux new, i have see the mips-kernel impement
> cache strategy: invalid and write-back,
> is it right?  is it implement the write-through strategy? see in
> include/asm-mips/r4kcache.h
> 
> how i can know the kernel using which cache strategy in user space, such
> as how can see the /proc system to know it?

The kernel will always use cache stategy 3 for non-coherent systems and
caching strategy 5 for cache coherent systems.  These two select the most
aggressive caching strategy on all processors and that's what gives the
best performance.

I think write through is just not worth thinking about it.  Early 4K
cores did only implement write through; later models added write-back and
as the result have significantly improved performance.

Minor optimizations of the cacheflush operations for write-through caches
would be possible but I expect only small gains.  R4kcache.h implements a
bunch of helper functions that iterate over memory areas; optimizations
for write-through caches should be done by the callers of these helper
functions.

Again, if you have write-back caches don't even think about write-though.
It almost certainly less effective.

  Ralf

  reply	other threads:[~2009-11-18 11:44 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-11-18  2:59 how i can know the linux-mips implememt cache strategy? figo zhang
2009-11-18 11:44 ` Ralf Baechle [this message]
2009-11-21 15:18   ` Shane McDonald
2009-11-21 23:31     ` Ralf Baechle

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