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Date:   Wed, 25 Nov 2009 15:01:41 +0000
From:   Ralf Baechle <ralf@linux-mips.org>
To:     Arnaud Patard <arnaud.patard@rtp-net.org>
Cc:     Florian Lohoff <flo@rfc822.org>,
        Aurelien Jarno <aurelien@aurel32.net>,
        linux-mips@linux-mips.org
Subject: Re: Syncing CPU caches from userland on MIPS
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On Wed, Nov 25, 2009 at 03:39:01PM +0100, Arnaud Patard wrote:

> > Would this only evict stuff from the ICACHE? When trying to execute
> > a just written buffer and with a writeback DCACHE you would need to 
> > explicitly writeback the DCACHE to memory and invalidate the ICACHE.
> 
> we already though about using BCACHE instead of ICACHE only but it
> didn't make any difference. the bug is still there.

That argument is ignored; the kernel will always do whatever it takes to
get the I-cache consistent.

  Ralf