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Date:   Wed, 13 Jan 2010 13:33:34 +0100
From:   Ralf Baechle <ralf@linux-mips.org>
To:     David Daney <ddaney@caviumnetworks.com>
Cc:     linux-mips@linux-mips.org
Subject: Re: [PATCH 2/2] MIPS: Octeon: Use optimized memory barrier
 primitives.
Message-ID: <20100113123334.GB20354@linux-mips.org>
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On Fri, Jan 08, 2010 at 05:17:44PM -0800, David Daney wrote:

> In order to achieve correct synchronization semantics, the Octeon port
> had defined CONFIG_WEAK_REORDERING_BEYOND_LLSC.  This resulted in code
> that looks like:
> 
>    sync
>    ll ...
>    .
>    .
>    .
>    sc ...
>    .
>    .
>    sync
> 
> The second SYNC was redundant, but harmless.
> 
> Octeon has a SYNCW instruction that acts as a write-memory-barrier
> (due to an erratum in some parts two SYNCW are used).  It is much
> faster than SYNC because it imposes ordering on the writes, but
> doesn't otherwise stall the execution pipeline.  On Octeon, SYNC
> stalls execution until all preceeding writes are committed to the
> coherent memory system.
> 
> Using:
> 
>     syncw;syncw
>     ll
>     .
>     .
>     .
>     sc
>     .
>     .
> 
> Has identical semantics to the first sequence, but is much faster.
> The SYNCW orders the writes, and the SC will not complete successfully
> until the write is committed to the coherent memory system.  So at the
> end all preceeding writes have been committed.  Since Octeon does not
> do speculative reads, this functions as a full barrier.
> 
> The patch removes CONFIG_WEAK_REORDERING_BEYOND_LLSC, and substitutes
> SYNCW for SYNC in write-memory-barriers.

Queued for 2.6.34.  Thanks!

  Ralf