From: Ralf Baechle <ralf@linux-mips.org>
To: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: Bcm47xx: Fix 128MB RAM support
Date: Mon, 22 Feb 2010 20:14:40 +0100 [thread overview]
Message-ID: <20100222191440.GA12818@linux-mips.org> (raw)
In-Reply-To: <1266691880-372-1-git-send-email-hauke@hauke-m.de>
On Sat, Feb 20, 2010 at 07:51:20PM +0100, Hauke Mehrtens wrote:
> Ignoring the last page when ddr size is 128M. Cached
> accesses to last page is causing the processor to prefetch
> using address above 128M stepping out of the ddr address
> space.
Is this a hardware issue prefetching issue? The kernel should not try
CPU prefetch instructions at all on non-coherent CPUs such as the
BCM47xx.
Ralf
next prev parent reply other threads:[~2010-02-22 19:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-02-20 18:51 [PATCH] MIPS: Bcm47xx: Fix 128MB RAM support Hauke Mehrtens
2010-02-22 19:14 ` Ralf Baechle [this message]
2010-02-22 20:25 ` Hauke Mehrtens
2010-02-22 20:36 ` Ralf Baechle
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