From: Ralf Baechle <ralf@linux-mips.org>
To: Maxime Bizon <mbizon@freebox.fr>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH v2 01/11] MIPS: BCM63XX: set default pci cache line size.
Date: Tue, 15 Nov 2011 19:54:38 +0000 [thread overview]
Message-ID: <20111115195438.GF26141@linux-mips.org> (raw)
In-Reply-To: <1320430175-13725-2-git-send-email-mbizon@freebox.fr>
On Fri, Nov 04, 2011 at 07:09:25PM +0100, Maxime Bizon wrote:
> + pci_cache_line_size = 4;
> +
Presumably because the CPU cache line size is 16 bytes? On MIPS we don't
set pci_dfl_cache_line_size; a patch (only compile tested) to pick a sane
default is below.
Does this work for you?
Ralf
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/pci/pci.c | 29 ++++++++++++++++++++++++++++-
1 files changed, 28 insertions(+), 1 deletions(-)
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 41af7fa..8ac0d48 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -4,8 +4,11 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
- * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2011 Wind River Systems,
+ * written by Ralf Baechle (ralf@linux-mips.org)
*/
+#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
@@ -14,6 +17,8 @@
#include <linux/types.h>
#include <linux/pci.h>
+#include <asm/cpu-info.h>
+
/*
* Indicate whether we respect the PCI setup left by the firmware.
*
@@ -150,10 +155,32 @@ out:
"Skipping PCI bus scan due to resource conflict\n");
}
+static void __init pcibios_set_cache_line_size(void)
+{
+ struct cpuinfo_mips *c = ¤t_cpu_data;
+ unsigned int lsize;
+
+ /*
+ * Set PCI cacheline size to that of the highest level in the
+ * cache hierarchy.
+ */
+ lsize = c->dcache.linesz;
+ lsize = c->scache.linesz ? : lsize;
+ lsize = c->tcache.linesz ? : lsize;
+
+ BUG_ON(!lsize);
+
+ pci_dfl_cache_line_size = lsize >> 2;
+
+ pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
+}
+
static int __init pcibios_init(void)
{
struct pci_controller *hose;
+ pcibios_set_cache_line_size();
+
/* Scan all of the recorded PCI controllers. */
for (hose = hose_head; hose; hose = hose->next)
pcibios_scanbus(hose);
next prev parent reply other threads:[~2011-11-15 19:54 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-11-04 18:09 [PATCH v2 00/11] MIPS: BCM63XX: add support for Broadcom 6368 CPU Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-04 18:09 ` [PATCH v2 01/11] MIPS: BCM63XX: set default pci cache line size Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-15 19:54 ` Ralf Baechle [this message]
2011-11-18 18:12 ` Maxime Bizon
2011-11-18 18:28 ` Ralf Baechle
2011-11-04 18:09 ` [PATCH v2 02/11] MIPS: BCM63XX: hook up plat_ioremap to intercept soc registers remapping Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-16 11:28 ` Ralf Baechle
2011-11-04 18:09 ` [PATCH v2 03/11] MIPS: BCM63XX: call board_register_device from device_initcall() Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-16 11:28 ` Ralf Baechle
2011-11-04 18:09 ` [PATCH v2 04/11] MIPS: BCM63XX: introduce bcm_readll & bcm_writell Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-05 20:54 ` Sergei Shtylyov
2011-11-16 11:29 ` Ralf Baechle
2011-11-04 18:09 ` [PATCH v2 05/11] MIPS: BCM63XX: cleanup cpu registers Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-16 11:29 ` Ralf Baechle
2011-11-04 18:09 ` [PATCH v2 06/11] MIPS: BCM63XX: add more register sets & missing register definitions Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-16 11:29 ` Ralf Baechle
2011-11-04 18:09 ` [PATCH v2 07/11] MIPS: BCM63XX: change irq code to prepare for per-cpu peculiarity Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-16 11:30 ` Ralf Baechle
2011-11-04 18:09 ` [PATCH v2 08/11] MIPS: BCM63XX: prepare irq code to handle different external irq hardware implementation Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-16 11:30 ` Ralf Baechle
2011-11-04 18:09 ` [PATCH v2 09/11] MIPS: BCM63XX: handle 64 bits irq stat register in irq code Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-16 11:30 ` Ralf Baechle
2011-11-04 18:09 ` [PATCH v2 10/11] MIPS: BCM63XX: add external irq support for non 6348 CPUs Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-09 12:35 ` Jonas Gorski
2011-11-16 11:33 ` Ralf Baechle
2011-11-18 18:40 ` [PATCH v3 " Maxime Bizon
2011-11-04 18:09 ` [PATCH v2 11/11] MIPS: BCM63XX: add support for bcm6368 CPU Maxime Bizon
2011-11-04 18:09 ` Maxime Bizon
2011-11-16 11:33 ` Ralf Baechle
2011-11-18 18:41 ` [PATCH v3 " Maxime Bizon
2011-11-09 12:43 ` [PATCH v2 00/11] MIPS: BCM63XX: add support for Broadcom 6368 CPU Jonas Gorski
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