From: Ralf Baechle <ralf@linux-mips.org>
To: Mikael Starvik <mikael.starvik@axis.com>
Cc: "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>
Subject: Re: SMP MIPS and Linux 3.2
Date: Tue, 21 Feb 2012 11:34:55 +0100 [thread overview]
Message-ID: <20120221103455.GA13347@linux-mips.org> (raw)
In-Reply-To: <4BEA3FF3CAA35E408EA55C7BE2E61D055C769FECBC@xmail3.se.axis.com>
On Mon, Feb 20, 2012 at 10:34:20AM +0100, Mikael Starvik wrote:
> I'm running Linux 3.2 on a MIPS 34K with two VPEs (in MT_SMP configuration). It works fine in UP but with SMP it deadlocks during bootup (both CPUs gets idle). Typically like this:
>
> [ 0.090000] CPU revision is: 01019550 (MIPS 34Kc)
> [ 0.090000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [ 0.090000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [ 0.170000] Brought up 2 CPUs
> <No more output>
>
> I have tried to enable __ARCH_WANT_INTERRUPTS_ON_CTXSW but that didn't
> improve anything. Anyone else got this running or have any thoughts about
> what the problem may be?
It used to work ... Are you testing this on Malta? In my experience if a
CPU hangs at this stage it often is because it does not receive a timer
tick, so all changes to the timer code are candidates to be reviewed.
Git bisect may be the way of least resistance here.
Ralf
next prev parent reply other threads:[~2012-02-21 10:35 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-02-20 9:34 SMP MIPS and Linux 3.2 Mikael Starvik
2012-02-21 2:11 ` tiejun.chen
2012-05-11 12:28 ` JoeJ
2012-02-21 10:34 ` Ralf Baechle [this message]
2012-02-21 15:33 ` John Crispin
-- strict thread matches above, loose matches on Subject: below --
2012-02-22 10:57 Mikael Starvik
2012-02-23 10:11 ` Deng-Cheng Zhu
2012-02-23 16:25 ` John Crispin
2012-02-24 7:53 ` Gandham, Raghu
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