From: Ralf Baechle <ralf@linux-mips.org>
To: "Steven J. Hill" <sjhill@mips.com>
Cc: linux-mips@linux-mips.org, sjhill@realitydiluted.com
Subject: Re: [PATCH 2/5] MIPS: Clean-up GIC and vectored interrupts.
Date: Wed, 30 May 2012 09:48:52 +0100 [thread overview]
Message-ID: <20120530084852.GA9324@linux-mips.org> (raw)
In-Reply-To: <1333735140-15719-1-git-send-email-sjhill@mips.com>
On Fri, Apr 06, 2012 at 12:59:00PM -0500, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> This change adds macros for routing of GIC interrupts for EIC and
> non-EIC hardware modes. Also added Malta GIC macros having to do
> with performance and timer interrupts.
>
> Signed-off-by: Steven J. Hill <sjhill@mips.com>
> diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
> index fb698dc..78dbb8a 100644
> --- a/arch/mips/include/asm/irq.h
> +++ b/arch/mips/include/asm/irq.h
> @@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq);
> * IE7. Since R2 their number has to be read from the c0_intctl register.
> */
> #define CP0_LEGACY_COMPARE_IRQ 7
> +#define CP0_LEGACY_PERFCNT_IRQ 7
>
> extern int cp0_compare_irq;
> extern int cp0_compare_irq_shift;
I split of this segment into a separate commit because it appeared to
be unrelated to the rest of the patch and also made use of the symbol
in traps.c.
Thanks,
Ralf
prev parent reply other threads:[~2012-05-30 8:49 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-06 17:59 [PATCH 2/5] MIPS: Clean-up GIC and vectored interrupts Steven J. Hill
2012-05-30 8:48 ` Ralf Baechle [this message]
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