From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Nov 2012 10:44:27 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58403 "EHLO linux-mips.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6820610Ab2KBJo0odKBD (ORCPT ); Fri, 2 Nov 2012 10:44:26 +0100 Received: from scotty.linux-mips.net (localhost.localdomain [127.0.0.1]) by scotty.linux-mips.net (8.14.5/8.14.4) with ESMTP id qA29iO9o023423; Fri, 2 Nov 2012 10:44:24 +0100 Received: (from ralf@localhost) by scotty.linux-mips.net (8.14.5/8.14.5/Submit) id qA29iNsr023422; Fri, 2 Nov 2012 10:44:23 +0100 Date: Fri, 2 Nov 2012 10:44:23 +0100 From: Ralf Baechle To: Jean-Christophe PINCE Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: MIPS ASID type conflicts Message-ID: <20121102094423.GB17860@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-archive-position: 34851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Return-Path: On Mon, Apr 23, 2012 at 01:49:26PM +0200, Jean-Christophe PINCE wrote: > I am analyzing Linux MIPS tasks memory spaces and found out what I > think is a bug in the ASID management. > > The structure "struct cpuinfo_mips" defined in > arch/mips/include/asm/cpu-info.h uses a "unsigned int" field for > asid_cache while the context field defined in > arch/mips/include/asm/mmu.h is a "unsigned long". > > This is ok with 32bits kernel but leads to 4bytes vs 8bytes fields > with a 64bits kernel. And when the scheduler checks if the ASID is of > an older ASID_VERSION, the test will always return that the version > differs when the context bits above bit31 will be set. > > I imagine this should be a quite rare issue but could likely happen on > devices running for very long and starting processes very often (or > running more than 256 processes per cpu). When this condition (bit 32 > or above of asid_cache is set), the effect should be that the TLB will > be flushed on each context_switch required by the scheduler but there > shouldn't be any crash. A full flush of the TLB can be implemented by picking a fresh ASID as long as there are still fresh ASIDs available. This happens fairly frequently; a typical system has burned through the first 256 ASIDs somewhen during bootup. There is not much advantage to be gained from having the ASID and generation counter in a 64-bit variable so I think I'm just going to change mmu_context_t to: typedef struct { unsigned int asid[NR_CPUS]; void *vdso; } mm_context_t; Ralf