From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Apr 2013 12:30:20 +0200 (CEST) Received: from fw-tnat.cambridge.arm.com ([217.140.96.21]:33258 "EHLO cam-smtp0.cambridge.arm.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6835166Ab3DPKaT56lfO (ORCPT ); Tue, 16 Apr 2013 12:30:19 +0200 Received: from arm.com (e106165-lin.cambridge.arm.com [10.1.197.23]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id r3GAU6PJ012078; Tue, 16 Apr 2013 11:30:06 +0100 Date: Tue, 16 Apr 2013 11:30:06 +0100 From: Andrew Murray To: "linux-mips@linux-mips.org" , "linuxppc-dev@lists.ozlabs.org" Cc: "rob.herring@calxeda.com" , "jgunthorpe@obsidianresearch.com" , "linux@arm.linux.org.uk" , "siva.kallam@samsung.com" , "linux-pci@vger.kernel.org" , "devicetree-discuss@lists.ozlabs.org" , "jg1.han@samsung.com" , Liviu Dudau , "linux-kernel@vger.kernel.org" , "linux-samsung-soc@vger.kernel.org" , "kgene.kim@samsung.com" , "bhelgaas@google.com" , "suren.reddy@samsung.com" , "linux-arm-kernel@lists.infradead.org" , "monstr@monstr.eu" , "benh@kernel.crashing.org" , "paulus@samba.org" , "grant.likely@secretlab.ca" , "thomas.petazzoni@free-electrons.com" , "thierry.reding@avionic-design.de" , "thomas.abraham@linaro.org" , "arnd@arndb.de" , "linus.walleij@linaro.org" Subject: Re: [PATCH v7 1/3] of/pci: Unify pci_process_bridge_OF_ranges from Microblaze and PowerPC Message-ID: <20130416103005.GB12726@arm.com> References: <1366107508-12672-1-git-send-email-Andrew.Murray@arm.com> <1366107508-12672-2-git-send-email-Andrew.Murray@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1366107508-12672-2-git-send-email-Andrew.Murray@arm.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 36239 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: andrew.murray@arm.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On Tue, Apr 16, 2013 at 11:18:26AM +0100, Andrew Murray wrote: > The pci_process_bridge_OF_ranges function, used to parse the "ranges" > property of a PCI host device, is found in both Microblaze and PowerPC > architectures. These implementations are nearly identical. This patch > moves this common code to a common place. > > Signed-off-by: Andrew Murray > Signed-off-by: Liviu Dudau > Reviewed-by: Rob Herring > Tested-by: Thomas Petazzoni > Tested-by: Linus Walleij > Acked-by: Michal Simek > --- > arch/microblaze/include/asm/pci-bridge.h | 5 +- > arch/microblaze/pci/pci-common.c | 192 ---------------------------- > arch/powerpc/include/asm/pci-bridge.h | 5 +- > arch/powerpc/kernel/pci-common.c | 192 ---------------------------- Is there anyone on linuxppc-dev/linux-mips that can help test this patchset? I've tested that it builds on powerpc with a variety of configs (some which include fsl_pci.c implementation). Though I don't have hardware to verify that it works. I haven't tested this builds or runs on MIPS. You shouldn't see any difference in behaviour or new warnings and PCI devices should continue to operate as before. Andrew Murray From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fw-tnat.cambridge.arm.com ([217.140.96.21]:33258 "EHLO cam-smtp0.cambridge.arm.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S6835166Ab3DPKaT56lfO (ORCPT ); Tue, 16 Apr 2013 12:30:19 +0200 Date: Tue, 16 Apr 2013 11:30:06 +0100 From: Andrew Murray Subject: Re: [PATCH v7 1/3] of/pci: Unify pci_process_bridge_OF_ranges from Microblaze and PowerPC Message-ID: <20130416103005.GB12726@arm.com> References: <1366107508-12672-1-git-send-email-Andrew.Murray@arm.com> <1366107508-12672-2-git-send-email-Andrew.Murray@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1366107508-12672-2-git-send-email-Andrew.Murray@arm.com> Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: "linux-mips@linux-mips.org" , "linuxppc-dev@lists.ozlabs.org" Cc: "rob.herring@calxeda.com" , "jgunthorpe@obsidianresearch.com" , "linux@arm.linux.org.uk" , "siva.kallam@samsung.com" , "linux-pci@vger.kernel.org" , "devicetree-discuss@lists.ozlabs.org" , "jg1.han@samsung.com" , Liviu Dudau , "linux-kernel@vger.kernel.org" , "linux-samsung-soc@vger.kernel.org" , "kgene.kim@samsung.com" , "bhelgaas@google.com" , "suren.reddy@samsung.com" , "linux-arm-kernel@lists.infradead.org" , "monstr@monstr.eu" , "benh@kernel.crashing.org" , "paulus@samba.org" , "grant.likely@secretlab.ca" , "thomas.petazzoni@free-electrons.com" , "thierry.reding@avionic-design.de" , "thomas.abraham@linaro.org" , "arnd@arndb.de" , "linus.walleij@linaro.org" Message-ID: <20130416103006.RxPsuxYF-NqE5LfI_6vKN9o-_b7bP3POWZZDwV5osEs@z> On Tue, Apr 16, 2013 at 11:18:26AM +0100, Andrew Murray wrote: > The pci_process_bridge_OF_ranges function, used to parse the "ranges" > property of a PCI host device, is found in both Microblaze and PowerPC > architectures. These implementations are nearly identical. This patch > moves this common code to a common place. > > Signed-off-by: Andrew Murray > Signed-off-by: Liviu Dudau > Reviewed-by: Rob Herring > Tested-by: Thomas Petazzoni > Tested-by: Linus Walleij > Acked-by: Michal Simek > --- > arch/microblaze/include/asm/pci-bridge.h | 5 +- > arch/microblaze/pci/pci-common.c | 192 ---------------------------- > arch/powerpc/include/asm/pci-bridge.h | 5 +- > arch/powerpc/kernel/pci-common.c | 192 ---------------------------- Is there anyone on linuxppc-dev/linux-mips that can help test this patchset? I've tested that it builds on powerpc with a variety of configs (some which include fsl_pci.c implementation). Though I don't have hardware to verify that it works. I haven't tested this builds or runs on MIPS. You shouldn't see any difference in behaviour or new warnings and PCI devices should continue to operate as before. Andrew Murray