From: Ralf Baechle <ralf@linux-mips.org>
To: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org, Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Subject: Re: [PATCH] MIPS: Add printing of ES bit when cache error occurs.
Date: Tue, 8 Oct 2013 07:06:33 +0200 [thread overview]
Message-ID: <20131008050633.GD1615@linux-mips.org> (raw)
In-Reply-To: <1381137952-18340-1-git-send-email-markos.chandras@imgtec.com>
On Mon, Oct 07, 2013 at 10:25:52AM +0100, Markos Chandras wrote:
> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>
> Print out the source of request that caused the error (ES bit) when
> a cache error exception occurs.
The reason ES isn't being printed is that not all processors that support
a cache error exception have an ES bit. The R4000 has it, R5000 doesn't,
R10000 CacheErr looks rather different - and in fact MIPS32/64 make the
entire register optional and its details implementation specific.
Don't even ask me anymore which processor the implementation in the
kernel is trying to support - probably something R7000ish, at least
that's what guess from the 1385617929e09545f9858785ea3dc1068fedfde1
commit log.
Short of some fancy engineering, I'd suggest throwing in a switch
statement and per processor type printks just as in parity_protection_init.
Ralf
next prev parent reply other threads:[~2013-10-08 5:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-07 9:25 [PATCH] MIPS: Add printing of ES bit when cache error occurs Markos Chandras
2013-10-07 9:25 ` Markos Chandras
2013-10-08 5:06 ` Ralf Baechle [this message]
2013-10-08 8:16 ` Markos Chandras
2013-10-08 8:16 ` Markos Chandras
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