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From: Ralf Baechle <ralf@linux-mips.org>
To: Yong Zhang <yong.zhang0@gmail.com>
Cc: Yong Zhang <yong.zhang@windriver.com>,
	linux-mips@linux-mips.org, huawei.libin@huawei.com
Subject: Re: [PATCH] MIPS: change type of asid_cache to unsigned long
Date: Thu, 22 May 2014 15:42:45 +0200	[thread overview]
Message-ID: <20140522134245.GF10287@linux-mips.org> (raw)
In-Reply-To: <20140522020611.GA6813@zhy>

On Thu, May 22, 2014 at 10:06:11AM +0800, Yong Zhang wrote:

> On Wed, May 21, 2014 at 01:29:36PM +0200, Ralf Baechle wrote:
> > On Wed, May 21, 2014 at 01:38:53PM +0800, Yong Zhang wrote:
> > 
> > > Please check the V2 in which I add the reporter.
> > > And thanks libin for reporting it :)
> > 
> > The bug was introduced in 5636919b5c909fee54a6ef5226475ecae012ad02
> > [MIPS: Outline udelay and fix a few issues.] in 2009 btw.  I think
> > the intension was to avoid holes in the structure and minimize
> > the bloat.  I instead applied aptch
> 
> Could you please show the patch?
> 
> > which also moves another member
> > of the struct arond such that no hole will be created in the struct.
> > This is important because the strcture it accessed fairly frequently
> > so we want to fit the most important members into as few cache
> > lines as possible.
> 
> I have tried to move the struct member around, but I found that the
> hole cann't be avoided completely because for exampe struct cache_desc
> is a bit special.

Yes, struct cache_desc is still a problem.  Easily solvable though -
some of it's members are excessivly large; by using smaller data types
both the struct and its required alignment will shrink.  But that's
for another patch; as for this patch my goal to just not make things
any worse.

  Ralf

---
 arch/mips/include/asm/cpu-info.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index dc2135b..ff2707a 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -39,14 +39,14 @@ struct cache_desc {
 #define MIPS_CACHE_PINDEX	0x00000020	/* Physically indexed cache */
 
 struct cpuinfo_mips {
-	unsigned int		udelay_val;
-	unsigned int		asid_cache;
+	unsigned long		asid_cache;
 
 	/*
 	 * Capability and feature descriptor structure for MIPS CPU
 	 */
 	unsigned long		options;
 	unsigned long		ases;
+	unsigned int		udelay_val;
 	unsigned int		processor_id;
 	unsigned int		fpu_id;
 	unsigned int		msa_id;

  reply	other threads:[~2014-05-22 13:43 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-20  8:09 [PATCH] MIPS: change type of asid_cache to unsigned long Yong Zhang
2014-05-21  5:38 ` Yong Zhang
2014-05-21  5:38   ` Yong Zhang
2014-05-21 11:29   ` Ralf Baechle
2014-05-22  2:06     ` Yong Zhang
2014-05-22 13:42       ` Ralf Baechle [this message]
2014-05-23  3:08         ` Yong Zhang
2014-08-27 22:52         ` David Daney

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