From: Ralf Baechle <ralf@linux-mips.org>
To: David Daney <ddaney.cavm@gmail.com>
Cc: Huacai Chen <chenhc@lemote.com>, John Crispin <john@phrozen.org>,
"Steven J. Hill" <Steven.Hill@imgtec.com>,
Aurelien Jarno <aurelien@aurel32.net>,
linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>
Subject: Re: [PATCH V2 4/8] MIPS: Add NUMA support for Loongson-3
Date: Wed, 4 Jun 2014 08:46:01 +0200 [thread overview]
Message-ID: <20140604064601.GU5157@linux-mips.org> (raw)
In-Reply-To: <538E5EA8.8010907@gmail.com>
On Tue, Jun 03, 2014 at 04:47:52PM -0700, David Daney wrote:
> On 06/03/2014 03:47 PM, Ralf Baechle wrote:
> [...]
> >>--- a/arch/mips/include/asm/addrspace.h
> >>+++ b/arch/mips/include/asm/addrspace.h
> >>@@ -51,8 +51,14 @@
> >> * Returns the physical address of a CKSEGx / XKPHYS address
> >> */
> >> #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
> >>+
> >>+#ifndef CONFIG_NUMA
> >> #define XPHYSADDR(a) ((_ACAST64_(a)) & \
> >> _CONST64_(0x000000ffffffffff))
> >>+#else
> >>+#define XPHYSADDR(a) ((_ACAST64_(a)) & \
> >>+ _CONST64_(0x0000ffffffffffff))
> >>+#endif
> >
> >The mask in XPHYSADDR is a function of the processor architecture, not
> >imlementation, not NUMA. The latest version of the MIPS architecture
> >permits PABITS to be as large as 49 bits, so the mask should be
> >0x0001ffffffffffff. Always.
> >
> >>diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
> >>index d2da53c..c001a90 100644
> >>--- a/arch/mips/include/asm/sparsemem.h
> >>+++ b/arch/mips/include/asm/sparsemem.h
> >>@@ -11,7 +11,12 @@
> >> #else
> >> # define SECTION_SIZE_BITS 28
> >> #endif
> >>+
> >>+#ifdef CONFIG_NUMA
> >>+#define MAX_PHYSMEM_BITS 48
> >>+#else
> >> #define MAX_PHYSMEM_BITS 35
> >>+#endif
> >
> >Essentially the same comment as for XPHYSADDR above.
>
> Are you saying to change it to 49 unconditionally for all configurations?
>
> That would work for OCTEON too, where we have had to increase it to 42.
>
> What are the implications for kernel data structures if this is set
> many orders of magnitude greater than the actual number of bits used
> on a system?
Shouldn't make a significant difference; the value is used to compute certain
limits in sparse.c and a bitmap in zsmalloc.c which is used only when
CONFIG_ZSMALLOC is enabled.
A more important value which I haven't noticed the Looongson patches to
modify is SECTION_SIZE_BITS in <asm/sparsemem.h>:
#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && defined(CONFIG_PAGE_SIZE_64KB)
# define SECTION_SIZE_BITS 29
#else
# define SECTION_SIZE_BITS 28
#endif
Don't ask me why its definition depends on MIPS_HUGE_TLB_SUPPORT and
PAGE_SIZE_64KB - the value describes the larges chunk of contiguous
memory (that is for example memory per node) and that doesn't depend
on these CONFIG_* symbols.
Ralf
next prev parent reply other threads:[~2014-06-04 6:46 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-13 0:24 [PATCH V2 0/8] MIPS: Loongson-3: Add NUMA and Loongson-3B support Huacai Chen
2014-04-13 0:24 ` [PATCH V2 1/8] MIPS: Support hard limit of cpu count (nr_cpu_ids) Huacai Chen
2014-04-14 14:48 ` Andreas Herrmann
2014-04-13 0:24 ` [PATCH V2 2/8] MIPS: Support CPU topology files in sysfs Huacai Chen
2014-04-14 15:04 ` Andreas Herrmann
2014-04-13 0:24 ` [PATCH V2 3/8] MIPS: Loongson: Modify ChipConfig register definition Huacai Chen
2014-04-13 0:24 ` [PATCH V2 4/8] MIPS: Add NUMA support for Loongson-3 Huacai Chen
2014-06-03 22:47 ` Ralf Baechle
2014-06-03 23:47 ` David Daney
2014-06-04 6:46 ` Ralf Baechle [this message]
2014-06-04 17:22 ` David Daney
2014-06-05 9:15 ` Huacai Chen
2014-04-13 0:24 ` [PATCH V2 5/8] MIPS: Add numa api support Huacai Chen
2014-04-13 0:24 ` [PATCH V2 6/8] MIPS: Add Loongson-3B support Huacai Chen
2014-04-13 0:24 ` [PATCH V2 7/8] MIPS: Loongson-3: Enable the COP2 usage Huacai Chen
2014-04-13 0:24 ` [PATCH V2 8/8] MIPS: Loongson: Rename CONFIG_LEMOTE_MACH3A to CONFIG_LOONGSON_MACH3X Huacai Chen
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