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From: Ralf Baechle <ralf@linux-mips.org>
To: Paul Burton <paul.burton@imgtec.com>
Cc: Ed Swierk <eswierk@skyportsystems.com>,
	linux-mips@linux-mips.org, ddaney.cavm@gmail.com
Subject: Re: [PATCH v2 5/6] mips: use per-mm page to execute FP branch delay slots
Date: Fri, 4 Jul 2014 11:38:09 +0200	[thread overview]
Message-ID: <20140704093809.GI13532@linux-mips.org> (raw)
In-Reply-To: <20140704090601.GZ804@pburton-laptop>

On Fri, Jul 04, 2014 at 10:06:01AM +0100, Paul Burton wrote:

> > The actual piece of code that needs to be installed is tiny.  So the page
> > could be shared between many threads.  In fact a single page would
> > suffice for most processes and only threads would require more slots
> > than provided by a single page so more pags could be allocated or the
> > process could sleep until a slot becomes available.
> 
> You just roughly described the v2 patch that we're replying to :)

Can't be that wrong then :-)

I seem to only have replies to that patch in my mail folder not the
patch itself.

> The problem is how to reliably free the frame after it has been used.
> I can see ways to do it, but none that are particularly "nice".
> 
> > Assuming the smallest supported page size of 4k and slots of 128 bytes
> > (that is the largest S-cache line size in common use) that's 32 slots.
> 
> Why S-cache line sized slots? I suppose it could simplify updating the
> page slightly at the cost of space.

That's to handle the worst case - R4000/R4400 SC and MC variants it is
possible to split the S-cache as SI-cache and SD-cache.  That means
modified instructions need to be written back all the way to memory
otherwise potencially stale instructions might be fetched from the
SI-cache.

That's more theoretical - I'm not aware of any system that's using split
S-caches.  Still using S-cache line sized slots might reduce the cache
line ping pong on multi-core systems a bit.

> > I'm also wondering how insane emulation would be.  We already have the
> > capability to emulate a fair fraction of the instruction set.
> 
> Yeah, and I'm reasonably sure we're going to need some more once MIPSr6
> is supported. I guess (perhaps only for the short term?) it could be
> done in stages - if systems include ASEs or cop2 that the emulation
> didn't implement then it could fall back to the current emuframe code.

And it's dependence on executable stackframe ...

> I'm in 2 minds about this - it sounds crazy but perhaps it's the most
> sane option available :)

Sanity is overrated anyway ;-)

  Ralf

  parent reply	other threads:[~2014-07-04  9:38 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-03 22:31 [PATCH v2 5/6] mips: use per-mm page to execute FP branch delay slots Ed Swierk
2014-07-04  8:06 ` Paul Burton
2014-07-04  8:06   ` Paul Burton
2014-07-04  8:52   ` Ralf Baechle
2014-07-04  9:06     ` Paul Burton
2014-07-04  9:06       ` Paul Burton
2014-07-04  9:38       ` Ralf Baechle [this message]
2014-07-04 11:30         ` Paul Burton
2014-07-04 11:30           ` Paul Burton
2014-07-04 15:42           ` Ralf Baechle
2014-09-13 23:06           ` Maciej W. Rozycki
2014-09-18  8:57             ` Paul Burton
2014-09-18  8:57               ` Paul Burton
  -- strict thread matches above, loose matches on Subject: below --
2014-07-03 17:56 Ed Swierk
2014-07-03 20:12 ` Paul Burton
2014-07-03 20:12   ` Paul Burton
2013-11-08 12:07 [PATCH " Paul Burton
2013-11-08 14:50 ` [PATCH v2 " Paul Burton
2013-11-08 14:50   ` Paul Burton
2013-11-21 16:48   ` Paul Burton
2013-11-21 16:48     ` Paul Burton

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