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[46.59.216.211]) by mx.google.com with ESMTPSA id pi8sm2170899wic.17.2014.09.25.00.34.36 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Sep 2014 00:34:37 -0700 (PDT) Date: Thu, 25 Sep 2014 09:34:36 +0200 From: Thierry Reding To: Yijing Wang Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Xinwei Hu , Wuyun , linux-arm-kernel@lists.infradead.org, Russell King , linux-arch@vger.kernel.org, arnab.basu@freescale.com, Bharat.Bhushan@freescale.com, x86@kernel.org, Arnd Bergmann , Thomas Gleixner , Konrad Rzeszutek Wilk , xen-devel@lists.xenproject.org, Joerg Roedel , iommu@lists.linux-foundation.org, linux-mips@linux-mips.org, Benjamin Herrenschmidt , linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, Sebastian Ott , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org, Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , Sergei Shtylyov , Michael Ellerman , Thomas Petazzoni Subject: Re: [PATCH v2 12/22] MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq Message-ID: <20140925073435.GJ12423@ulmo> References: <1411614872-4009-1-git-send-email-wangyijing@huawei.com> <1411614872-4009-13-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="rwgQ89ZNnFUwFHTC" Content-Disposition: inline In-Reply-To: <1411614872-4009-13-git-send-email-wangyijing@huawei.com> User-Agent: Mutt/1.5.23 (2014-03-12) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 42802 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thierry.reding@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips --rwgQ89ZNnFUwFHTC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Sep 25, 2014 at 11:14:22AM +0800, Yijing Wang wrote: [...] > diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c [...] > @@ -132,12 +132,12 @@ msi_irq_allocated: > /* Make sure the search for available interrupts didn't fail */ > if (irq >=3D 64) { > if (request_private_bits) { > - pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying= just one", > + pr_err("octeon_setup_msi_irq: Unable to find %d free interrupts, tryi= ng just one", > 1 << request_private_bits); Perhaps while at it make this (and other similar changes in this patch): pr_err("%s(): Unable to ...", __func__, ...); So that it becomes more resilient against this kind of rename? > request_private_bits =3D 0; > goto try_only_one; > } else > - panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); > + panic("octeon_setup_msi_irq: Unable to find a free MSI interrupt"); > @@ -210,14 +210,13 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nv= ec, int type) > =20 > return 0; > } > - This... > @@ -240,7 +239,7 @@ void arch_teardown_msi_irq(unsigned int irq) > */ > number_irqs =3D 0; > while ((irq0 + number_irqs < 64) && > - (msi_multiple_irq_bitmask[index] > + (msi_multiple_irq_bitmask[index] =2E.. and this seem like unrelated whitespace changes. > & (1ull << (irq0 + number_irqs)))) > number_irqs++; > number_irqs++; > @@ -249,8 +248,8 @@ void arch_teardown_msi_irq(unsigned int irq) > /* Shift the mask to the correct bit location */ > bitmask <<=3D irq0; > if ((msi_free_irq_bitmask[index] & bitmask) !=3D bitmask) > - panic("arch_teardown_msi_irq: Attempted to teardown MSI " > - "interrupt (%d) not in use", irq); > + panic("octeon_teardown_msi_irq: Attempted to teardown MSI " > + "interrupt (%d) not in use", irq); And the second line here also needlessly changes the indentation. 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