From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
stable@vger.kernel.org,
Markos Chandras <markos.chandras@imgtec.com>,
James Hogan <james.hogan@imgtec.com>,
linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 3.17 007/122] MIPS: cpu-probe: Set the FTLB probability bit on supported cores
Date: Fri, 5 Dec 2014 14:43:01 -0800 [thread overview]
Message-ID: <20141205223306.616304416@linuxfoundation.org> (raw)
In-Reply-To: <20141205223305.514276242@linuxfoundation.org>
3.17-stable review patch. If anyone has any objections, please let me know.
------------------
From: Markos Chandras <markos.chandras@imgtec.com>
commit cf0a8aa0226da5de88011e7f30eff22a894b2f49 upstream.
Make use of the Config6/FLTBP bit to set the probability of a TLBWR
instruction to hit the FTLB or the VTLB. A value of 0 (which may be
the default value on certain cores, such as proAptiv or P5600)
means that a TLBWR instruction will never hit the VTLB which
leads to performance limitations since it effectively decreases
the number of available TLB slots.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8368/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/include/asm/mipsregs.h | 2 ++
arch/mips/kernel/cpu-probe.c | 33 ++++++++++++++++++++++++++++++++-
2 files changed, 34 insertions(+), 1 deletion(-)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -661,6 +661,8 @@
#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
/* proAptiv FTLB on/off bit */
#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
+/* FTLB probability bits */
+#define MIPS_CONF6_FTLBP_SHIFT (16)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -192,6 +192,32 @@ static void set_isa(struct cpuinfo_mips
static char unknown_isa[] = KERN_ERR \
"Unsupported ISA type, c0.config0: %d.";
+static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
+{
+
+ unsigned int probability = c->tlbsize / c->tlbsizevtlb;
+
+ /*
+ * 0 = All TLBWR instructions go to FTLB
+ * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
+ * FTLB and 1 goes to the VTLB.
+ * 2 = 7:1: As above with 7:1 ratio.
+ * 3 = 3:1: As above with 3:1 ratio.
+ *
+ * Use the linear midpoint as the probability threshold.
+ */
+ if (probability >= 12)
+ return 1;
+ else if (probability >= 6)
+ return 2;
+ else
+ /*
+ * So FTLB is less than 4 times bigger than VTLB.
+ * A 3:1 ratio can still be useful though.
+ */
+ return 3;
+}
+
static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
{
unsigned int config6;
@@ -202,9 +228,14 @@ static void set_ftlb_enable(struct cpuin
case CPU_P5600:
/* proAptiv & related cores use Config6 to enable the FTLB */
config6 = read_c0_config6();
+ /* Clear the old probability value */
+ config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
if (enable)
/* Enable FTLB */
- write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
+ write_c0_config6(config6 |
+ (calculate_ftlb_probability(c)
+ << MIPS_CONF6_FTLBP_SHIFT)
+ | MIPS_CONF6_FTLBEN);
else
/* Disable FTLB */
write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
next prev parent reply other threads:[~2014-12-05 22:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20141205223305.514276242@linuxfoundation.org>
2014-12-05 22:42 ` [PATCH 3.17 002/122] MIPS: lib: memcpy: Restore NOP on delay slot before returning to caller Greg Kroah-Hartman
2014-12-05 22:42 ` [PATCH 3.17 003/122] MIPS: oprofile: Fix backtrace on 64-bit kernel Greg Kroah-Hartman
2014-12-05 22:42 ` [PATCH 3.17 004/122] MIPS: tlb-r4k: Add missing HTW stop/start sequences Greg Kroah-Hartman
2014-12-05 22:42 ` [PATCH 3.17 005/122] MIPS: Loongson3: Fix __node_distances undefined error Greg Kroah-Hartman
2014-12-05 22:43 ` [PATCH 3.17 006/122] MIPS: asm: uaccess: Add v1 register to clobber list on EVA Greg Kroah-Hartman
2014-12-05 22:43 ` Greg Kroah-Hartman [this message]
2014-12-05 22:43 ` [PATCH 3.17 008/122] MIPS: fix EVA & non-SMP non-FPU FP context signal handling Greg Kroah-Hartman
2014-12-05 22:43 ` [PATCH 3.17 009/122] MIPS: r4kcache: Add EVA case for protected_writeback_dcache_line Greg Kroah-Hartman
2014-12-05 22:43 ` [PATCH 3.17 010/122] MIPS: tlbex: Fix potential HTW race on TLBL/M/S handlers Greg Kroah-Hartman
2014-12-05 22:43 ` [PATCH 3.17 011/122] MIPS: Loongson: Make platform serial setup always built-in Greg Kroah-Hartman
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