From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Markos Chandras <markos.chandras@imgtec.com>,
linux-mips@linux-mips.org,
"Maciej W. Rozycki" <macro@linux-mips.org>,
Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 4.0 16/72] MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
Date: Mon, 11 May 2015 10:54:22 -0700 [thread overview]
Message-ID: <20150511175437.598355085@linuxfoundation.org> (raw)
In-Reply-To: <20150511175437.112151861@linuxfoundation.org>
4.0-stable review patch. If anyone has any objections, please let me know.
------------------
From: Markos Chandras <markos.chandras@imgtec.com>
Commit f6b39ae6f4d6ee835bb16e452086121aa010f1a7 upstream.
Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll
functions") added support for MIPS R6 cache flushes but it used the
wrong base address register to perform the flushes so the same lines
were flushed over and over. Moreover, replace the "addiu" instructions
with LONG_ADDIU so the correct base address is calculated for 64-bit
cores.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions")
Cc: linux-mips@linux-mips.org
Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9384/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/include/asm/r4kcache.h | 89 +++++++++++++++++++--------------------
1 file changed, 45 insertions(+), 44 deletions(-)
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -12,6 +12,8 @@
#ifndef _ASM_R4KCACHE_H
#define _ASM_R4KCACHE_H
+#include <linux/stringify.h>
+
#include <asm/asm.h>
#include <asm/cacheops.h>
#include <asm/compiler.h>
@@ -344,7 +346,7 @@ static inline void invalidate_tcache_pag
" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \
" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \
" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \
- " addiu $1, $0, 0x100 \n" \
+ " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x010($1)\n" \
" cache %1, 0x020($1); cache %1, 0x030($1)\n" \
" cache %1, 0x040($1); cache %1, 0x050($1)\n" \
@@ -368,17 +370,17 @@ static inline void invalidate_tcache_pag
" cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \
" cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \
" cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \
- " addiu $1, %0, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x020($1)\n" \
" cache %1, 0x040($1); cache %1, 0x060($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
- " addiu $1, $1, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x020($1)\n" \
" cache %1, 0x040($1); cache %1, 0x060($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
- " addiu $1, $1, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100\n" \
" cache %1, 0x000($1); cache %1, 0x020($1)\n" \
" cache %1, 0x040($1); cache %1, 0x060($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
@@ -396,25 +398,25 @@ static inline void invalidate_tcache_pag
" .set noat\n" \
" cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \
" cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \
- " addiu $1, %0, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
- " addiu $1, %0, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
- " addiu $1, %0, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
- " addiu $1, %0, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
- " addiu $1, %0, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
- " addiu $1, %0, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
- " addiu $1, %0, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
" cache %1, 0x000($1); cache %1, 0x040($1)\n" \
" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
" .set pop\n" \
@@ -429,39 +431,38 @@ static inline void invalidate_tcache_pag
" .set mips64r6\n" \
" .set noat\n" \
" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
- " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
- " addiu $1, %0, 0x100\n" \
+ " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
+ " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
+ " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
" .set pop\n" \
: \
: "r" (base), \
next prev parent reply other threads:[~2015-05-11 17:58 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20150511175437.112151861@linuxfoundation.org>
2015-05-11 17:54 ` [PATCH 4.0 07/72] MIPS: BCM63xx: Move bcm63xx_gpio_init() to bcm63xx_register_devices() Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 08/72] MIPS: OCTEON: dma-octeon: fix OHCI USB config check Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 09/72] MIPS: OCTEON: Use correct CSR to soft reset Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 10/72] Revert "MIPS: Remove race window in page fault handling" Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 11/72] MIPS: Fix race condition in lazy cache flushing Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 12/72] MIPS: Octeon: Remove udelay() causing huge IRQ latency Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 13/72] MIPS: OCTEON: fix PCI interrupt mapping for D-Link DSR-1000N Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 14/72] MIPS: Netlogic: Fix for SATA PHY init Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 15/72] MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter Greg Kroah-Hartman
2015-05-11 17:54 ` Greg Kroah-Hartman [this message]
2015-05-11 17:54 ` [PATCH 4.0 17/72] MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 18/72] MIPS: kernel: entry.S: Set correct ISA level for mips_ihb Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 22/72] SSB: fix Kconfig dependencies Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 23/72] MIPS: ralink: Fix bad config symbol in PCI makefile Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 24/72] MIPS: ralink: add missing symbol for RALINK_ILL_ACC Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 25/72] MIPS: smp-cps: cpu_set FPU mask if FPU present Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 26/72] MIPS: Kconfig: Disable SMP/CPS for 64-bit Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 27/72] MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 28/72] MIPS: asm: elf: Set O32 default FPU flags Greg Kroah-Hartman
2015-05-11 17:54 ` [PATCH 4.0 29/72] MIPS: Makefile: Fix MIPS ASE detection code Greg Kroah-Hartman
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