From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
stable@vger.kernel.org, Paul Burton <paul.burton@imgtec.com>,
Markos Chandras <markos.chandras@imgtec.com>,
linux-mips@linux-mips.org, James Hogan <james.hogan@imgtec.com>,
Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 4.2 018/134] MIPS: CPS: use 32b accesses to GCRs
Date: Sat, 26 Sep 2015 13:54:30 -0700 [thread overview]
Message-ID: <20150926205312.900382098@linuxfoundation.org> (raw)
In-Reply-To: <20150926205311.819185658@linuxfoundation.org>
4.2-stable review patch. If anyone has any objections, please let me know.
------------------
From: Paul Burton <paul.burton@imgtec.com>
commit 90996511187d6282db6d02d3f97006b4dbb5c457 upstream.
Commit b677bc03d757 ("MIPS: cps-vec: Use macros for various arithmetics
and memory operations") replaced various load & store instructions
through cps-vec.S with the PTR_L & PTR_S macros. However it was somewhat
overzealous in doing so for CM GCR accesses, since the bit width of the
CM doesn't necessarily match that of the CPU. The registers accessed
(GCR_CL_COHERENCE & GCR_CL_ID) should be safe to simply always access
using 32b instructions, so do so in order to avoid issues when using a
32b CM with a 64b CPU.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/10864/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/kernel/cps-vec.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -152,7 +152,7 @@ dcache_done:
/* Enter the coherent domain */
li t0, 0xff
- PTR_S t0, GCR_CL_COHERENCE_OFS(v1)
+ sw t0, GCR_CL_COHERENCE_OFS(v1)
ehb
/* Jump to kseg0 */
@@ -302,7 +302,7 @@ LEAF(mips_cps_boot_vpes)
PTR_L t0, 0(t0)
/* Calculate a pointer to this cores struct core_boot_config */
- PTR_L t0, GCR_CL_ID_OFS(t0)
+ lw t0, GCR_CL_ID_OFS(t0)
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
PTR_LA t1, mips_cps_core_bootcfg
next parent reply other threads:[~2015-09-26 20:57 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20150926205311.819185658@linuxfoundation.org>
2015-09-26 20:54 ` Greg Kroah-Hartman [this message]
2015-09-26 20:54 ` [PATCH 4.2 019/134] MIPS: math-emu: Allow m{f,t}hc emulation on MIPS R6 Greg Kroah-Hartman
2015-09-26 20:54 ` [PATCH 4.2 020/134] MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructions Greg Kroah-Hartman
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