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From: Ralf Baechle <ralf@linux-mips.org>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: Petri Gynther <pgynther@google.com>,
	linux-mips@linux-mips.org, f.fainelli@gmail.com,
	cernekee@gmail.com
Subject: Re: [PATCH] MIPS: switch BMIPS5000 to use r4k_wait_irqoff()
Date: Tue, 12 Jan 2016 14:27:53 +0100	[thread overview]
Message-ID: <20160112132753.GA30362@linux-mips.org> (raw)
In-Reply-To: <alpine.LFD.2.20.1601120038000.23714@eddie.linux-mips.org>

On Tue, Jan 12, 2016 at 12:42:14AM +0000, Maciej W. Rozycki wrote:

> > > Programming notes:
> > > The WAIT instruction should be executed while interrupts are disabled
> > > by the IE bit in the Status register. This avoids a potential timing
> > > hazard, which occurs if an interrupt is taken between testing the counter
> > > and executing the WAIT instruction. In this hazard case, the interrupt
> > > will have been completed before the WAIT instruction is executed, so
> > > the processor will remain indefinitely in wait state until the next
> > > interrupt.
> > 
> > Note that this is the opposite restriction than many older MIPS CPUs
> > where it is undefined if an interrupt will restart execution of
> > instructions if interrupts are disabled.  So this might be a violation
> > of the architecture specification.  However I rather have it the BMIPS
> > way than the other way ...
> 
>  It's been implementation-dependent since MIPSr1 whether a non-enabled 
> interrupt breaks out of WAIT, so no architecture specification violation 
> here.

I probably should have clarified that in the commit message but alas
too late, this commit is long upstream.

  Ralf

      reply	other threads:[~2016-01-12 13:27 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-19 18:44 [PATCH] MIPS: switch BMIPS5000 to use r4k_wait_irqoff() Petri Gynther
2015-10-20  3:18 ` Florian Fainelli
2015-11-02 20:54   ` Petri Gynther
2015-11-09  9:24 ` Ralf Baechle
2016-01-12  0:42   ` Maciej W. Rozycki
2016-01-12 13:27     ` Ralf Baechle [this message]

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