From: James Hogan <james.hogan@imgtec.com>
To: Huacai Chen <chenhc@lemote.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
Aurelien Jarno <aurelien@aurel32.net>,
"Steven J. Hill" <Steven.Hill@imgtec.com>,
Linux MIPS Mailing List <linux-mips@linux-mips.org>,
Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>
Subject: Re: [PATCH 5/6] MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature
Date: Wed, 27 Jan 2016 11:15:57 +0000 [thread overview]
Message-ID: <20160127111557.GA19682@jhogan-linux.le.imgtec.org> (raw)
In-Reply-To: <CAAhV-H5zFb=rnESwHvgykNVe1FyAC1WX5zAHUXswYwu7a=VPKw@mail.gmail.com>
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Hi Huacai,
On Wed, Jan 27, 2016 at 12:58:42PM +0800, Huacai Chen wrote:
> "cache coherency" here means the coherency across cores, not ic/dc
> coherency, could you please suggest a suitable name?
Data cache coherency across cores is pretty much a requirement for SMP.
It looks more like for various reasons you can skip the cache management
functions, e.g.
> >> @@ -503,6 +509,9 @@ static void r4k_flush_cache_range(struct vm_area_struct *vma,
> >> {
> >> int exec = vma->vm_flags & VM_EXEC;
> >>
> >> + if (cpu_has_coherent_cache)
> >> + return;
This seems to suggest:
1) Your dcaches don't alias.
2) Your icache is coherent with your dcache, otherwise you would need to
flush the icache here so that mprotect RW->RX makes code executable
without risk of stale lines existing in icache.
So, is that the case?
If so, it would seem better to ensure that cpu_has_dc_aliases evaluates
to false, and add a similar one for icache coherency, hence my original
suggestion.
> >> +
> >> if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
> >> r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
(Note, this cpu_has_ic_fills_f_dc check is wrong, it shouldn't prevent
icache flush, see http://patchwork.linux-mips.org/patch/12179/)
Cheers
James
> >> }
> >> @@ -627,6 +636,9 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
> >> {
> >> struct flush_cache_page_args args;
> >>
> >> + if (cpu_has_coherent_cache)
> >> + return;
> >> +
> >> args.vma = vma;
> >> args.addr = addr;
> >> args.pfn = pfn;
> >> @@ -636,11 +648,17 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
> >>
> >> static inline void local_r4k_flush_data_cache_page(void * addr)
> >> {
> >> + if (cpu_has_coherent_cache)
> >> + return;
> >> +
> >> r4k_blast_dcache_page((unsigned long) addr);
> >> }
> >>
> >> static void r4k_flush_data_cache_page(unsigned long addr)
> >> {
> >> + if (cpu_has_coherent_cache)
> >> + return;
> >> +
> >> if (in_atomic())
> >> local_r4k_flush_data_cache_page((void *)addr);
> >> else
> >> @@ -825,6 +843,9 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
> >>
> >> static void r4k_flush_cache_sigtramp(unsigned long addr)
> >> {
> >> + if (cpu_has_coherent_cache)
> >> + return;
> >> +
> >> r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
> >> }
> >>
> >> --
> >> 2.4.6
> >>
> >>
> >>
> >>
> >>
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next prev parent reply other threads:[~2016-01-27 11:16 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-26 13:26 [PATCH 0/6] MIPS: Loongson: Add Loongson-3A R2 support Huacai Chen
2016-01-26 13:26 ` [PATCH 1/6] MIPS: Loongson: Add Loongson-3A R2 basic support Huacai Chen
2016-01-26 13:26 ` [PATCH 2/6] MIPS: Loongson: Invalidate special TLBs when needed Huacai Chen
2016-01-26 13:26 ` [PATCH 3/6] MIPS: Loongson-3: Fast TLB refill handler Huacai Chen
2016-01-26 13:26 ` [PATCH 4/6] MIPS: tlbex: Fix bugs in tlbchange handler Huacai Chen
2016-01-26 21:15 ` David Daney
2016-01-27 4:53 ` Huacai Chen
2016-01-27 5:50 ` Joshua Kinard
2016-01-27 10:22 ` Joshua Kinard
2016-01-26 13:26 ` [PATCH 5/6] MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature Huacai Chen
2016-01-26 13:42 ` James Hogan
2016-01-26 13:42 ` James Hogan
2016-01-27 4:58 ` Huacai Chen
2016-01-27 11:15 ` James Hogan [this message]
2016-01-28 7:38 ` Huacai Chen
2016-01-26 13:26 ` [PATCH 6/6] MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT Huacai Chen
2016-01-26 14:19 ` James Hogan
2016-01-26 14:19 ` James Hogan
2016-01-27 5:02 ` Huacai Chen
2016-01-27 11:18 ` James Hogan
2016-01-28 7:48 ` Huacai Chen
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