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Date:   Wed, 10 Feb 2016 10:20:33 +0100
From:   Ralf Baechle <ralf@linux-mips.org>
To:     Florian Fainelli <f.fainelli@gmail.com>
Cc:     linux-mips@linux-mips.org, blogic@openwrt.org, cernekee@gmail.com,
        jon.fraser@broadcom.com, pgynther@google.com,
        paul.burton@imgtec.com, ddaney.cavm@gmail.com
Subject: Re: [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs
Message-ID: <20160210092033.GB10352@linux-mips.org>
References: <1455051354-6225-1-git-send-email-f.fainelli@gmail.com>
 <1455051354-6225-2-git-send-email-f.fainelli@gmail.com>
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On Tue, Feb 09, 2016 at 12:55:49PM -0800, Florian Fainelli wrote:

> +static void bmips5000_pref30_quirk(void)
> +{
> +	__asm__ __volatile__(
> +	"	.word	0x4008b008\n"	/* mfc0 $8, $22, 8 */
> +	"	lui	$9, 0x0100\n"
> +	"	or	$8, $9\n"
> +	/* disable "pref 30" on buggy CPUs */
> +	"	lui	$9, 0x0800\n"
> +	"	or	$8, $9\n"
> +	"	.word	0x4088b008\n"	/* mtc0 $8, $22, 8 */
> +	: : : "$8", "$9");
> +}

Simpler:

#define read_c0_horse_with_no_name(val)  __read_32bit_c0_register($22, 8, val)
#define write_c0_horse_with_no_name(val) __write_32bit_c0_register($22, 8)

...

write_c0_horse_with_no_name(read_c0_horse_with_no_name() | 0x123);

And why do both MFC0 and MTC0 instructions above have the same opcode?
Also the selector number used above for both instructions is 8 - but the
architecture only allows for 8 selectors 0..7.

  Ralf