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Date:   Wed, 10 Feb 2016 10:22:16 +0100
From:   Ralf Baechle <ralf@linux-mips.org>
To:     Florian Fainelli <f.fainelli@gmail.com>
Cc:     linux-mips@linux-mips.org, blogic@openwrt.org, cernekee@gmail.com,
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        paul.burton@imgtec.com, ddaney.cavm@gmail.com
Subject: Re: [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs
Message-ID: <20160210092216.GC10352@linux-mips.org>
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On Wed, Feb 10, 2016 at 10:20:33AM +0100, Ralf Baechle wrote:

> And why do both MFC0 and MTC0 instructions above have the same opcode?

Forget this one, I should occasionally open my eyes in the morning ;)

  Ralf