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From: Aurelien Jarno <aurelien@aurel32.net>
To: linux-mips@linux-mips.org
Subject: Emulation of unaligned LDXC1/SDXC1 instructions
Date: Thu, 21 Apr 2016 12:19:23 +0200	[thread overview]
Message-ID: <20160421101923.GA24852@aurel32.net> (raw)

Hi all,

Debian recently got access to Cavium III machines which have an FPU,
before we were using Cavium II machines with the kernel FPU emulation.

It appears some code (at least openjdk and lcms2, probably more) use the
LDXC1 and SDXC1 instructions with word aligned addresses instead of
double-word aligned addresses as required by the specification. This
causes a SIGILL. The kernel emulation is more relaxed and allow word
aligned addresses.

First of all I am surprised to get a SIGILL in that case instead of a
SIGBUS, and secondly I think the behavior with and without FPU should be
consistent. The kernel currently emulates unaligned LDC1 and SDC1
instructions even with an FPU, so I wonder if the kernel should also
emulate unaligned LDXC1 and SDXC1 instructions.

Any opinion?

Thanks,
Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

             reply	other threads:[~2016-04-21 10:19 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-21 10:19 Aurelien Jarno [this message]
2016-04-21 11:25 ` [PATCH] MIPS: Allow emulation for unaligned [LS]DXC1 instructions Paul Burton
2016-04-21 11:25   ` Paul Burton
2016-04-21 14:59   ` Aurelien Jarno

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