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Date:   Tue, 10 May 2016 17:40:02 +0200
From:   Ralf Baechle <ralf@linux-mips.org>
To:     James Hogan <james.hogan@imgtec.com>
Cc:     linux-mips@linux-mips.org, Matt Redfearn <Matt.Redfearn@imgtec.com>
Subject: Re: [PATCH 2/5] MIPS: Add defs & probing of 64-bit CP0_EBase
Message-ID: <20160510154002.GH16402@linux-mips.org>
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On Tue, May 10, 2016 at 04:34:35PM +0100, James Hogan wrote:

> On Tue, May 10, 2016 at 12:24:06PM +0200, Ralf Baechle wrote:
> > On Tue, May 10, 2016 at 11:02:09AM +0100, James Hogan wrote:
> > 
> > > On Fri, Apr 29, 2016 at 02:46:00PM +0100, James Hogan wrote:
> > > > MIPS64r2 and later cores may optionally have a 64-bit CP0_EBase
> > > > register, with a write gate (WG) bit to allow the upper half to be
> > > > written. The presence of this feature will need to be known about for VZ
> > > > support in order to correctly save and restore the guest CP0_EBase
> > > > register, so add CPU feature definitions and probing for this
> > > > capability.
> > > 
> > > Okay, so it turns out EBase.WG can be present on MIPS32 too, to allow
> > > writing of bits 31:30 (thanks Matt!), so this needs a little more
> > > thought.
> > 
> > So drop the series for now or do you want to patch it up later?
> 
> Yes, please drop it. I'll submit a v2 which probes for WG instead (i.e.
> detects it on MIPS32 too).

Done.

  Ralf