From: Ralf Baechle <ralf@linux-mips.org>
To: James Hogan <james.hogan@imgtec.com>
Cc: Matt Redfearn <matt.redfearn@imgtec.com>, linux-mips@linux-mips.org
Subject: Re: [PATCH 1/9] MIPS: traps: 64bit kernels should read CP0_EBase 64bit
Date: Wed, 21 Sep 2016 15:08:52 +0200 [thread overview]
Message-ID: <20160921130852.GA10899@linux-mips.org> (raw)
In-Reply-To: <e826225b15736539cd96a1b6b2a99e2bb2b4eb87.1472747205.git-series.james.hogan@imgtec.com>
On Thu, Sep 01, 2016 at 05:30:07PM +0100, James Hogan wrote:
> When reading the CP0_EBase register containing the WG (write gate) bit,
> the ebase variable should be set to the full value of the register, i.e.
> on a 64-bit kernel the full 64-bit width of the register via
> read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width
> including bits 31:30 which may be writeable.
How about changing the definition of read/write_c0_ebase to
#define read_c0_ebase() __read_ulong_c0_register($15, 1)
#define write_c0_ebase(val) __write_ulong_c0_register($15, 1, val)
or using a new variant like
#define read_c0_ebase_ulong() __read_ulong_c0_register($15, 1)
#define write_c0_ebase_ulong(val) __write_ulong_c0_register($15, 1, val)
to avoid the ifdefery? This could also make this bit
ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
: (s32)read_c0_ebase();
in cpu-probe.c prettier.
Ralf
next prev parent reply other threads:[~2016-09-21 13:09 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-01 16:30 [PATCH 0/9] MIPS: General EVA fixes & cleanups James Hogan
2016-09-01 16:30 ` [PATCH 1/9] MIPS: traps: 64bit kernels should read CP0_EBase 64bit James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-21 13:08 ` Ralf Baechle [this message]
2016-09-21 15:01 ` Matt Redfearn
2016-09-21 15:01 ` Matt Redfearn
2016-10-02 10:30 ` Maciej W. Rozycki
2016-10-05 15:56 ` James Hogan
2016-10-05 15:56 ` James Hogan
2016-10-06 16:18 ` Maciej W. Rozycki
2016-10-06 18:05 ` James Hogan
2016-10-06 18:05 ` James Hogan
2016-10-06 19:56 ` Maciej W. Rozycki
2016-10-06 20:19 ` James Hogan
2016-10-06 20:19 ` James Hogan
2016-10-06 22:41 ` Maciej W. Rozycki
2016-10-06 22:50 ` James Hogan
2016-10-06 22:50 ` James Hogan
2016-10-06 23:07 ` Maciej W. Rozycki
2016-10-07 15:35 ` David Daney
2016-10-07 15:41 ` David Daney
2016-10-07 17:39 ` Maciej W. Rozycki
2016-09-01 16:30 ` [PATCH 2/9] MIPS: traps: Convert ebase to KSeg0 James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-01 16:30 ` [PATCH 3/9] MIPS: traps: Ensure full EBase is written James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-21 13:19 ` Ralf Baechle
2016-09-01 16:30 ` [PATCH 4/9] MIPS: c-r4k: Drop bc_wback_inv() from icache flush James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-01 16:30 ` [PATCH 5/9] MIPS: c-r4k: Split user/kernel flush_icache_range() James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-01 16:30 ` [PATCH 6/9] MIPS: cacheflush: Use __flush_icache_user_range() James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-01 16:30 ` [PATCH 7/9] MIPS: uprobes: Flush icache via kernel address James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-21 13:26 ` Ralf Baechle
2016-09-21 18:15 ` Leonid Yegoshin
2016-09-21 18:15 ` Leonid Yegoshin
2016-09-22 21:15 ` James Hogan
2016-09-22 21:15 ` James Hogan
2016-09-22 21:38 ` Leonid Yegoshin
2016-09-22 21:38 ` Leonid Yegoshin
2016-09-22 21:42 ` Leonid Yegoshin
2016-09-22 21:42 ` Leonid Yegoshin
2016-09-22 22:13 ` James Hogan
2016-09-22 22:27 ` Leonid Yegoshin
2016-09-22 22:27 ` Leonid Yegoshin
2016-09-23 7:10 ` James Hogan
2016-09-01 16:30 ` [PATCH 8/9] MIPS: KVM: Use __local_flush_icache_user_range() James Hogan
2016-09-01 16:30 ` [PATCH 9/9] MIPS: c-r4k: Fix flush_icache_range() for EVA James Hogan
2016-09-01 16:30 ` James Hogan
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