From: Dan Carpenter <dan.carpenter@oracle.com>
To: blogic@openwrt.org
Cc: linux-mips@linux-mips.org
Subject: [bug report] MIPS: lantiq: implement support for FALCON soc
Date: Wed, 7 Dec 2016 23:04:55 +0300 [thread overview]
Message-ID: <20161207200455.GA25376@elgon.mountain> (raw)
Hello John Crispin,
The patch d41ced01f21d: "MIPS: lantiq: implement support for FALCON
soc" from Apr 19, 2012, leads to the following static checker warning:
arch/mips/lantiq/falcon/sysctrl.c:152 falcon_gpe_enable()
warn: mask and shift to zero
arch/mips/lantiq/falcon/sysctrl.c
140 /* enable the ONU core */
141 static void falcon_gpe_enable(void)
142 {
143 unsigned int freq;
144 unsigned int status;
145
146 /* if if the clock is already enabled */
147 status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC);
148 if (status & (1 << (GPPC_OFFSET + 1)))
149 return;
150
151 freq = (status_r32(STATUS_CONFIG) &
152 GPEFREQ_MASK) >>
153 GPEFREQ_OFFSET;
The mask is 0xC0 and we >> 10 which means that freq is always zero.
154 if (freq == 0)
155 freq = 1; /* use 625MHz on unfused chip */
So we always use 625MHz.
156
157 /* apply new frequency */
158 sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
159 freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
160 udelay(1);
161
162 /* enable new frequency */
163 sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
164 udelay(1);
165 }
regards,
dan carpenter
next reply other threads:[~2016-12-07 20:17 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-07 20:04 Dan Carpenter [this message]
2016-12-07 20:35 ` [bug report] MIPS: lantiq: implement support for FALCON soc John Crispin
-- strict thread matches above, loose matches on Subject: below --
2016-07-13 15:51 Dan Carpenter
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