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Date:   Tue, 21 Mar 2017 20:55:00 +0100
From:   Ralf Baechle <ralf@linux-mips.org>
To:     James Hogan <james.hogan@imgtec.com>
Cc:     linux-mips@linux-mips.org, Paolo Bonzini <pbonzini@redhat.com>,
        Radim =?utf-8?B?S3LEjW3DocWZ?= <rkrcmar@redhat.com>,
        kvm@vger.kernel.org
Subject: Re: [PATCH 2/2] KVM: MIPS/Emulate: Properly implement TLBR for T&E
Message-ID: <20170321195500.GB9697@linux-mips.org>
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On Tue, Mar 14, 2017 at 05:00:08PM +0000, James Hogan wrote:

> Properly implement emulation of the TLBR instruction for Trap & Emulate.
> This instruction reads the TLB entry pointed at by the CP0_Index
> register into the other TLB registers, which may have the side effect of
> changing the current ASID. Therefore abstract the CP0_EntryHi and ASID
> changing code into a common function in the process.
> 
> A comment indicated that Linux doesn't use TLBR, which is true during
> normal use, however dumping of the TLB does use it (for example with the
> relatively recent 'x' magic sysrq key), as does a wired TLB entries test
> case in my KVM tests.

Acked-by: Ralf Baechle <ralf@linux-mips.org>

  Ralf