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Date:   Thu, 15 Jun 2017 11:59:38 +0200
From:   Ralf Baechle <ralf@linux-mips.org>
To:     Huacai Chen <chenhc@lemote.com>
Cc:     John Crispin <john@phrozen.org>,
        "Steven J . Hill" <Steven.Hill@cavium.com>,
        linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
        Zhangjin Wu <wuzhangjin@gmail.com>, stable@vger.kernel.org
Subject: Re: [PATCH V5 2/9] MIPS: c-r4k: Add r4k_blast_scache_node for
 Loongson-3
Message-ID: <20170615095938.GA1391@linux-mips.org>
References: <1497492952-23877-1-git-send-email-chenhc@lemote.com>
 <1497492952-23877-3-git-send-email-chenhc@lemote.com>
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On Thu, Jun 15, 2017 at 10:15:45AM +0800, Huacai Chen wrote:

> For multi-node Loongson-3 (NUMA configuration), r4k_blast_scache() can
> only flush Node-0's scache. So we add r4k_blast_scache_node() by using
> (CAC_BASE | (node_id << NODE_ADDRSPACE_SHIFT)) instead of CKSEG0 as the
> start address.
> 
> Maybe all MIPS CPUs need r4k_blast_scache_node() to support cc-NUMA,
> but I don't know how to implement it for non-Loongson CPUs.

There other MIPS ccNUMA systems handle caches in hardware fully transparent
to software so no changes are required.  These systems are SGI's SN
(Origin, Onyx) and BCM1480 (ccNUMA support out of tree, but no sw support
required)).

  Ralf