From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 13 Aug 2017 06:37:54 +0200 (CEST) Received: from mailapp01.imgtec.com ([195.59.15.196]:37766 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23991978AbdHMEhoqudYd (ORCPT ); Sun, 13 Aug 2017 06:37:44 +0200 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id AF9DFE99A91E3; Sun, 13 Aug 2017 05:37:36 +0100 (IST) Received: from localhost (10.20.79.142) by hhmail02.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Sun, 13 Aug 2017 05:37:38 +0100 From: Paul Burton To: , Jason Cooper , Marc Zyngier , Thomas Gleixner CC: Ralf Baechle , James Hogan , Paul Burton , , Subject: [PATCH 01/38] irqchip: mips-gic: SYNC after enabling GIC region Date: Sat, 12 Aug 2017 21:36:09 -0700 Message-ID: <20170813043646.25821-2-paul.burton@imgtec.com> X-Mailer: git-send-email 2.14.0 In-Reply-To: <20170813043646.25821-1-paul.burton@imgtec.com> References: <20170813043646.25821-1-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.20.79.142] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 59517 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.burton@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips From: James Hogan A SYNC is required between enabling the GIC region and actually trying to use it, even if the first access is a read, otherwise its possible depending on the timing (and in my case depending on the precise alignment of certain kernel code) to hit CM bus errors on that first access. Add the SYNC straight after setting the GIC base. [paul.burton@imgtec.com: Changes later in this series increase our likelihood of hitting this by reducing the amount of code that runs between enabling the GIC & accessing it.] Fixes: a7057270c280 ("irqchip: mips-gic: Add device-tree support") Signed-off-by: James Hogan Signed-off-by: Paul Burton Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: Paul Burton Cc: Ralf Baechle Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: # 3.19.x- --- drivers/irqchip/irq-mips-gic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 9e984cefdca0..6841bd79c7c2 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -1022,6 +1022,9 @@ static int __init gic_of_init(struct device_node *node, if (mips_cm_present()) write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN); + /* Ensure GIC region is enabled before trying to access it */ + __sync(); + } gic_present = true; __gic_init(gic_base, gic_len, cpu_vec, 0, node); -- 2.14.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:37766 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23991978AbdHMEhoqudYd (ORCPT ); Sun, 13 Aug 2017 06:37:44 +0200 From: Paul Burton Subject: [PATCH 01/38] irqchip: mips-gic: SYNC after enabling GIC region Date: Sat, 12 Aug 2017 21:36:09 -0700 Message-ID: <20170813043646.25821-2-paul.burton@imgtec.com> In-Reply-To: <20170813043646.25821-1-paul.burton@imgtec.com> References: <20170813043646.25821-1-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: linux-mips@linux-mips.org, Jason Cooper , Marc Zyngier , Thomas Gleixner Cc: Ralf Baechle , James Hogan , Paul Burton , linux-kernel@vger.kernel.org, stable@vger.kernel.org Message-ID: <20170813043609.kkEEFHRrzNsde0Z5Wul_VU_6LTIiP_WdbJnDZDMrdfU@z> From: James Hogan A SYNC is required between enabling the GIC region and actually trying to use it, even if the first access is a read, otherwise its possible depending on the timing (and in my case depending on the precise alignment of certain kernel code) to hit CM bus errors on that first access. Add the SYNC straight after setting the GIC base. [paul.burton@imgtec.com: Changes later in this series increase our likelihood of hitting this by reducing the amount of code that runs between enabling the GIC & accessing it.] Fixes: a7057270c280 ("irqchip: mips-gic: Add device-tree support") Signed-off-by: James Hogan Signed-off-by: Paul Burton Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: Paul Burton Cc: Ralf Baechle Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: # 3.19.x- --- drivers/irqchip/irq-mips-gic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 9e984cefdca0..6841bd79c7c2 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -1022,6 +1022,9 @@ static int __init gic_of_init(struct device_node *node, if (mips_cm_present()) write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN); + /* Ensure GIC region is enabled before trying to access it */ + __sync(); + } gic_present = true; __gic_init(gic_base, gic_len, cpu_vec, 0, node); -- 2.14.0