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Date:   Thu, 2 Nov 2017 13:47:19 +0100
From:   Andrew Lunn <andrew@lunn.ch>
To:     Florian Fainelli <f.fainelli@gmail.com>
Cc:     David Daney <david.daney@cavium.com>, linux-mips@linux-mips.org,
        ralf@linux-mips.org, James Hogan <james.hogan@mips.com>,
        netdev@vger.kernel.org, "David S. Miller" <davem@davemloft.net>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        linux-kernel@vger.kernel.org,
        "Steven J. Hill" <steven.hill@cavium.com>,
        devicetree@vger.kernel.org, Carlos Munoz <cmunoz@cavium.com>
Subject: Re: [PATCH 1/7] dt-bindings: Add Cavium Octeon Common Ethernet
 Interface.
Message-ID: <20171102124719.GG4772@lunn.ch>
References: <20171102003606.19913-1-david.daney@cavium.com>
 <20171102003606.19913-2-david.daney@cavium.com>
 <af0de889-a34b-8346-9eeb-171498cc61ca@gmail.com>
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On Wed, Nov 01, 2017 at 06:09:17PM -0700, Florian Fainelli wrote:
> On 11/01/2017 05:36 PM, David Daney wrote:
> > From: Carlos Munoz <cmunoz@cavium.com>
> > 
> > Add bindings for Common Ethernet Interface (BGX) block.
> > 
> > Signed-off-by: Carlos Munoz <cmunoz@cavium.com>
> > Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com>
> > Signed-off-by: David Daney <david.daney@cavium.com>
> > ---
> [snip]
> > +Properties:
> > +
> > +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs.
> > +
> > +- reg: The index of the interface within the BGX block.
> > +
> > +- local-mac-address: Mac address for the interface.
> > +
> > +- phy-handle: phandle to the phy node connected to the interface.
> > +
> > +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting.
> > +  Needed by the Micrel PHY.
> 
> Is not that implied by an appropriate "phy-mode" property already?

Hi Florian

Looking at the driver patch, phy-mode is not used at
all. of_phy_connect() passes a hard coded SGMII value!

David, you need to fix this.

       Andrew