From: James Hogan <jhogan@kernel.org>
To: Sasha Levin <Alexander.Levin@microsoft.com>
Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Paul Burton <paul.burton@imgtec.com>,
"linux-mips@linux-mips.org" <linux-mips@linux-mips.org>,
Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH AUTOSEL for 4.9 173/293] MIPS: Handle tlbex-tlbp race condition
Date: Mon, 9 Apr 2018 21:42:29 +0100 [thread overview]
Message-ID: <20180409204229.GE17347@saruman> (raw)
In-Reply-To: <20180409002239.163177-173-alexander.levin@microsoft.com>
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On Mon, Apr 09, 2018 at 12:25:09AM +0000, Sasha Levin wrote:
> From: Paul Burton <paul.burton@imgtec.com>
>
> [ Upstream commit f39878cc5b09c75d35eaf52131e920b872e3feb4 ]
>
> In systems where there are multiple actors updating the TLB, the
> potential exists for a race condition wherein a CPU hits a TLB exception
> but by the time it reaches a TLBP instruction the affected TLB entry may
> have been replaced. This can happen if, for example, a CPU shares the
> TLB between hardware threads (VPs) within a core and one of them
> replaces the entry that another has just taken a TLB exception for.
>
> We handle this race in the case of the Hardware Table Walker (HTW) being
> the other actor already, but didn't take into account the potential for
> multiple threads racing. Include the code for aborting TLB exception
> handling in affected multi-threaded systems, those being the I6400 &
> I6500 CPUs which share TLB entries between VPs.
>
> In the case of using RiXi without dedicated exceptions we have never
> handled this race even for HTW. This patch adds WARN()s to these cases
> which ought never to be hit because all CPUs with either HTW or shared
> FTLB RAMs also include dedicated RiXi exceptions, but the WARN()s will
> ensure this is always the case.
...
> + /*
> + * If the CPU shares FTLB RAM with its siblings then our entry may be
> + * replaced at any time by a sibling performing a write to the FTLB.
> + */
> + if (cpu_has_shared_ftlb_ram)
cpu_has_shared_ftlb_ram was only added in v4.13, commit e7bc8557428f
("MIPS: Add CPU shared FTLB feature detection"). To backport this patch
you'd need that one too at least (and I6500 support was also new in 4.13
so you'd also have to drop that case from the backport of that patch).
There may be other dependencies too, I don't know OTOH.
Cheers
James
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next prev parent reply other threads:[~2018-04-09 20:42 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20180409002239.163177-1-alexander.levin@microsoft.com>
2018-04-09 0:22 ` [PATCH AUTOSEL for 4.9 008/293] MIPS: mm: fixed mappings: correct initialisation Sasha Levin
2018-04-09 0:22 ` [PATCH AUTOSEL for 4.9 009/293] MIPS: kprobes: flush_insn_slot should flush only if probe initialised Sasha Levin
2018-04-09 0:24 ` [PATCH AUTOSEL for 4.9 159/293] MIPS: module: Ensure we always clean up r_mips_hi16_list Sasha Levin
2018-04-09 0:24 ` [PATCH AUTOSEL for 4.9 160/293] MIPS: Give __secure_computing() access to syscall arguments Sasha Levin
2018-04-09 20:26 ` James Hogan
2018-04-09 0:24 ` [PATCH AUTOSEL for 4.9 161/293] MIPS: SEAD-3: Set interrupt-parent per-device, not at root node Sasha Levin
2018-04-09 0:25 ` [PATCH AUTOSEL for 4.9 169/293] MIPS: CPS: Prevent multi-core with dcache aliasing Sasha Levin
2018-04-09 0:25 ` [PATCH AUTOSEL for 4.9 170/293] MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse() Sasha Levin
2018-04-09 0:25 ` [PATCH AUTOSEL for 4.9 171/293] MIPS: CPS: Handle spurious VP starts more gracefully Sasha Levin
2018-04-09 0:25 ` [PATCH AUTOSEL for 4.9 172/293] MIPS: CPS: Handle cores not powering down " Sasha Levin
2018-04-09 0:25 ` [PATCH AUTOSEL for 4.9 173/293] MIPS: Handle tlbex-tlbp race condition Sasha Levin
2018-04-09 20:42 ` James Hogan [this message]
2018-04-09 0:25 ` [PATCH AUTOSEL for 4.9 174/293] MIPS: VDSO: Add implementation of clock_gettime() fallback Sasha Levin
2018-04-09 0:25 ` [PATCH AUTOSEL for 4.9 175/293] MIPS: VDSO: Add implementation of gettimeofday() fallback Sasha Levin
2018-04-09 0:25 ` [PATCH AUTOSEL for 4.9 230/293] clk: ingenic: Fix recalc_rate for clocks with fixed divider Sasha Levin
2018-04-09 0:26 ` [PATCH AUTOSEL for 4.9 273/293] MIPS: generic: Fix machine compatible matching Sasha Levin
2018-04-09 0:26 ` [PATCH AUTOSEL for 4.9 274/293] MIPS: TXx9: use IS_BUILTIN() for CONFIG_LEDS_CLASS Sasha Levin
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