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Tue, 12 Mar 2019 22:48:06 +0000 From: Hassan Naveed To: Paul Burton CC: "kafai@fb.com" , "songliubraving@fb.com" , "yhs@fb.com" , "netdev@vger.kernel.org" , "bpf@vger.kernel.org" , "linux-mips@vger.kernel.org" , Hassan Naveed , Ralf Baechle , Paul Burton , James Hogan , Alexei Starovoitov , Daniel Borkmann , "open list:MIPS" , open list Subject: [PATCH v2 2/3] MIPS: eBPF: Provide eBPF support for MIPS64R6 Thread-Topic: [PATCH v2 2/3] MIPS: eBPF: Provide eBPF support for MIPS64R6 Thread-Index: AQHU2SWozNoTqPTzRU+UcrV5QYZ6oQ== Date: Tue, 12 Mar 2019 22:48:06 +0000 Message-ID: <20190312224706.6121-2-hnaveed@wavecomp.com> References: <20190312224706.6121-1-hnaveed@wavecomp.com> In-Reply-To: <20190312224706.6121-1-hnaveed@wavecomp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR06CA0039.namprd06.prod.outlook.com (2603:10b6:a03:14b::16) To CY4PR2201MB1349.namprd22.prod.outlook.com (2603:10b6:910:64::23) authentication-results: spf=none (sender IP is ) smtp.mailfrom=hnaveed@wavecomp.com; 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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: +Wets5094GrFD1lhj1WmJPUboP8bjgoacgZTbU8i0HW3JTf3hdBmd4Nl+aGl3KvJKFl6kZ3Um6UErbn5OKfb1iBInX+uQ0cpUsF0AyK3xvetH4ZZp2cu1hgLCoG1702fMCoU13OjjhwqpYZKAkpu18zAhPINiZzw9n+bTa/tofbvnLrbqLQgC3LWzirezl51u5Tab2fei0jG1VBhfV7poL7f2CTtR6hFnVUqanzbB1cCW4otdXkXJzb9j5tBuDEsm2k6KkjwIkx8TLecTwif9E6XR/92NrUB8p7tfg8XvQaNXEWUd+AsmPpu4c0JEZOE3gfU2FeMADXioG5P1dJWXe2p+ms6rLkVfobHJl+gXk4vHxzYHXYMPR2QNCZQWECsBObHzCIXypovL9OWHuIABeHOC7btusDVbs6PkNiX1jI= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wavecomp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9ed2f9bb-472b-443e-8833-08d6a73cca98 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Mar 2019 22:48:06.1096 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR2201MB1720 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Currently eBPF support is available on MIPS64R2 only. Use MIPS64R6 variants of instructions like multiply, divide, movn, movz so eBPF can run on the newer ISA. Also, we only need to check ISA revision before JIT'ing code, because we know the CPU is running a 64-bit kernel because eBPF JIT is only included in kernels with CONFIG_64BIT=3Dy due to Kconfig dependencies. Signed-off-by: Hassan Naveed --- arch/mips/net/ebpf_jit.c | 78 +++++++++++++++++++++++++++++++++++----- 1 file changed, 69 insertions(+), 9 deletions(-) diff --git a/arch/mips/net/ebpf_jit.c b/arch/mips/net/ebpf_jit.c index 0effd3cba9a7..26eef9ad3896 100644 --- a/arch/mips/net/ebpf_jit.c +++ b/arch/mips/net/ebpf_jit.c @@ -22,6 +22,7 @@ #include #include #include +#include #include =20 /* Registers used by JIT */ @@ -677,8 +678,12 @@ static int build_one_insn(const struct bpf_insn *insn,= struct jit_ctx *ctx, if (insn->imm =3D=3D 1) /* Mult by 1 is a nop */ break; gen_imm_to_reg(insn, MIPS_R_AT, ctx); - emit_instr(ctx, dmultu, MIPS_R_AT, dst); - emit_instr(ctx, mflo, dst); + if (MIPS_ISA_REV >=3D 6) { + emit_instr(ctx, dmulu, dst, dst, MIPS_R_AT); + } else { + emit_instr(ctx, dmultu, MIPS_R_AT, dst); + emit_instr(ctx, mflo, dst); + } break; case BPF_ALU64 | BPF_NEG | BPF_K: /* ALU64_IMM */ dst =3D ebpf_to_mips_reg(ctx, insn, dst_reg); @@ -700,8 +705,12 @@ static int build_one_insn(const struct bpf_insn *insn,= struct jit_ctx *ctx, if (insn->imm =3D=3D 1) /* Mult by 1 is a nop */ break; gen_imm_to_reg(insn, MIPS_R_AT, ctx); - emit_instr(ctx, multu, dst, MIPS_R_AT); - emit_instr(ctx, mflo, dst); + if (MIPS_ISA_REV >=3D 6) { + emit_instr(ctx, mulu, dst, dst, MIPS_R_AT); + } else { + emit_instr(ctx, multu, dst, MIPS_R_AT); + emit_instr(ctx, mflo, dst); + } break; case BPF_ALU | BPF_NEG | BPF_K: /* ALU_IMM */ dst =3D ebpf_to_mips_reg(ctx, insn, dst_reg); @@ -732,6 +741,13 @@ static int build_one_insn(const struct bpf_insn *insn,= struct jit_ctx *ctx, break; } gen_imm_to_reg(insn, MIPS_R_AT, ctx); + if (MIPS_ISA_REV >=3D 6) { + if (bpf_op =3D=3D BPF_DIV) + emit_instr(ctx, divu_r6, dst, dst, MIPS_R_AT); + else + emit_instr(ctx, modu, dst, dst, MIPS_R_AT); + break; + } emit_instr(ctx, divu, dst, MIPS_R_AT); if (bpf_op =3D=3D BPF_DIV) emit_instr(ctx, mflo, dst); @@ -754,6 +770,13 @@ static int build_one_insn(const struct bpf_insn *insn,= struct jit_ctx *ctx, break; } gen_imm_to_reg(insn, MIPS_R_AT, ctx); + if (MIPS_ISA_REV >=3D 6) { + if (bpf_op =3D=3D BPF_DIV) + emit_instr(ctx, ddivu_r6, dst, dst, MIPS_R_AT); + else + emit_instr(ctx, modu, dst, dst, MIPS_R_AT); + break; + } emit_instr(ctx, ddivu, dst, MIPS_R_AT); if (bpf_op =3D=3D BPF_DIV) emit_instr(ctx, mflo, dst); @@ -819,11 +842,23 @@ static int build_one_insn(const struct bpf_insn *insn= , struct jit_ctx *ctx, emit_instr(ctx, and, dst, dst, src); break; case BPF_MUL: - emit_instr(ctx, dmultu, dst, src); - emit_instr(ctx, mflo, dst); + if (MIPS_ISA_REV >=3D 6) { + emit_instr(ctx, dmulu, dst, dst, src); + } else { + emit_instr(ctx, dmultu, dst, src); + emit_instr(ctx, mflo, dst); + } break; case BPF_DIV: case BPF_MOD: + if (MIPS_ISA_REV >=3D 6) { + if (bpf_op =3D=3D BPF_DIV) + emit_instr(ctx, ddivu_r6, + dst, dst, src); + else + emit_instr(ctx, modu, dst, dst, src); + break; + } emit_instr(ctx, ddivu, dst, src); if (bpf_op =3D=3D BPF_DIV) emit_instr(ctx, mflo, dst); @@ -903,6 +938,13 @@ static int build_one_insn(const struct bpf_insn *insn,= struct jit_ctx *ctx, break; case BPF_DIV: case BPF_MOD: + if (MIPS_ISA_REV >=3D 6) { + if (bpf_op =3D=3D BPF_DIV) + emit_instr(ctx, divu_r6, dst, dst, src); + else + emit_instr(ctx, modu, dst, dst, src); + break; + } emit_instr(ctx, divu, dst, src); if (bpf_op =3D=3D BPF_DIV) emit_instr(ctx, mflo, dst); @@ -1006,8 +1048,15 @@ static int build_one_insn(const struct bpf_insn *ins= n, struct jit_ctx *ctx, emit_instr(ctx, dsubu, MIPS_R_T8, dst, src); emit_instr(ctx, sltu, MIPS_R_AT, dst, src); /* SP known to be non-zero, movz becomes boolean not */ - emit_instr(ctx, movz, MIPS_R_T9, MIPS_R_SP, MIPS_R_T8); - emit_instr(ctx, movn, MIPS_R_T9, MIPS_R_ZERO, MIPS_R_T8); + if (MIPS_ISA_REV >=3D 6) { + emit_instr(ctx, seleqz, MIPS_R_T9, + MIPS_R_SP, MIPS_R_T8); + } else { + emit_instr(ctx, movz, MIPS_R_T9, + MIPS_R_SP, MIPS_R_T8); + emit_instr(ctx, movn, MIPS_R_T9, + MIPS_R_ZERO, MIPS_R_T8); + } emit_instr(ctx, or, MIPS_R_AT, MIPS_R_T9, MIPS_R_AT); cmp_eq =3D bpf_op =3D=3D BPF_JGT; dst =3D MIPS_R_AT; @@ -1366,6 +1415,17 @@ static int build_one_insn(const struct bpf_insn *ins= n, struct jit_ctx *ctx, if (src < 0) return src; if (BPF_MODE(insn->code) =3D=3D BPF_XADD) { + /* + * If mem_off does not fit within the 9 bit ll/sc + * instruction immediate field, use a temp reg. + */ + if (MIPS_ISA_REV >=3D 6 && + (mem_off >=3D BIT(8) || mem_off < -BIT(8))) { + emit_instr(ctx, daddiu, MIPS_R_T6, + dst, mem_off); + mem_off =3D 0; + dst =3D MIPS_R_T6; + } switch (BPF_SIZE(insn->code)) { case BPF_W: if (get_reg_val_type(ctx, this_idx, insn->src_reg) =3D=3D REG_32BIT) { @@ -1720,7 +1780,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog = *prog) unsigned int image_size; u8 *image_ptr; =20 - if (!prog->jit_requested || !cpu_has_mips64r2) + if (!prog->jit_requested || MIPS_ISA_REV < 2) return prog; =20 tmp =3D bpf_jit_blind_constants(prog); --=20 2.18.0