[RFC 0/5] MIPS: ralink: peripheral clock gating driver

[NOGUCHI Hiroshi <drvlabo@gmail.com>]

This series introduce Mediatek/Ralink SoC's clock gating driver.
The gating clock items are different at individual SoCs.
Driver loads gating clock item table defined in individual SoC source files,
via OF device id data.

NOGUCHI Hiroshi (5):
  mips: ralink: add rt2880-clock driver
  mips: ralink: add dt-binding document for rt2880-clock driver
  mips: ralink: mt7620/76x8 use clk framework and rt2880-clock driver
  mips: ralink: mt7628: add nodes for clock provider
  mips: ralink: mt7620: add nodes for clock provider

 .../bindings/clock/ralink,rt2880-clock.txt    |  20 +++
 arch/mips/boot/dts/ralink/mt7620a.dtsi        |  34 ++++-
 arch/mips/boot/dts/ralink/mt7628a.dtsi        |  37 +++++
 arch/mips/ralink/Kconfig                      |   6 +
 arch/mips/ralink/Makefile                     |   2 +
 arch/mips/ralink/clk.c                        |  30 ++++
 arch/mips/ralink/common.h                     |   3 +
 arch/mips/ralink/mt7620.c                     | 132 ++++++++++++++---
 arch/mips/ralink/rt2880-clk_internal.h        |  21 +++
 arch/mips/ralink/rt2880-clock.c               | 134 ++++++++++++++++++
 include/dt-bindings/clock/mt7620-clk.h        |  17 +++
 11 files changed, 411 insertions(+), 25 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
 create mode 100644 arch/mips/ralink/rt2880-clk_internal.h
 create mode 100644 arch/mips/ralink/rt2880-clock.c
 create mode 100644 include/dt-bindings/clock/mt7620-clk.h

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2.20.1