From: NOGUCHI Hiroshi <drvlabo@gmail.com>
To: John Crispin <john@phrozen.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-mips@vger.kernel.org, linux-clk@vger.kernel.org,
NOGUCHI Hiroshi <drvlabo@gmail.com>
Subject: [RFC 2/5] mips: ralink: add dt-binding document for rt2880-clock driver
Date: Sat, 30 Mar 2019 21:33:14 +0900 [thread overview]
Message-ID: <20190330123317.16821-3-drvlabo@gmail.com> (raw)
In-Reply-To: <20190330123317.16821-1-drvlabo@gmail.com>
Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
---
.../bindings/clock/ralink,rt2880-clock.txt | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt b/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
new file mode 100644
index 000000000000..6f0757046df4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
@@ -0,0 +1,20 @@
+* Clock bindings for Ralink/Mediatek MIPS based SoCs
+
+Required properties:
+ - compatible: must be "ralink,rt2880-clock" and
+ one of the following, to identify SoC series
+ "mediatek,mt7620-clock" for MT7620
+ "mediatek,mt7628-clock" for MT7628/MT7688
+ "mediatek,mt7621-clock" for MT7621
+ - #clock-cells: must be 1
+ - ralink,sysctl: a phandle to a ralink syscon register region
+
+
+Example:
+
+clkctrl: clkctrl {
+ compatible = "mediatek,mt7620-clock", "ralink,rt2880-clock";
+ #clock-cells = <1>;
+
+ ralink,sysctl = <&sysc>;
+};
--
2.20.1
next prev parent reply other threads:[~2019-03-30 12:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-30 12:33 [RFC 0/5] MIPS: ralink: peripheral clock gating driver NOGUCHI Hiroshi
2019-03-30 12:33 ` [RFC 1/5] mips: ralink: add rt2880-clock driver NOGUCHI Hiroshi
2019-04-02 20:08 ` Stephen Boyd
2019-03-30 12:33 ` NOGUCHI Hiroshi [this message]
2019-03-30 12:33 ` [RFC 3/5] mips: ralink: mt7620/76x8 use clk framework and " NOGUCHI Hiroshi
2019-04-02 20:18 ` Stephen Boyd
2019-03-30 12:33 ` [RFC 4/5] mips: ralink: mt7628: add nodes for clock provider NOGUCHI Hiroshi
2019-03-30 12:33 ` [RFC 5/5] mips: ralink: mt7620: " NOGUCHI Hiroshi
2019-04-02 20:32 ` Stephen Boyd
2019-04-01 7:21 ` [RFC 0/5] MIPS: ralink: peripheral clock gating driver John Crispin
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